boyzzun
Junior Member level 1
hi guys.i wrote code for adder 4 bit using '+" and '&' ,and i have error like this
and this is test
and error
how can i fix this error
PHP:
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.ALL;
use ieee.std_logic_unsigned.ALL;
entity add4 is
generic (N: natural := 32);
port ( A : in std_logic_vector(2 downto 0);
B : in std_logic_vector(2 downto 0);
Cin : in std_logic;
Sum : out std_logic_vector(2 downto 0);
Cout : out std_logic
);
end add4;
architecture dataflow of add4 is
signal A1 : std_logic_vector(3 downto 0);
signal B1 : std_logic_vector(3 downto 0);
signal Sum1: std_logic_vector(3 downto 0);
begin
A1 <= '0' & A;
B1 <= '0' & B;
Sum1 <= A1 + B1 + Cin;
Cout <= Sum1(3);
Sum <= Sum1(2 downto 0);
end dataflow;
PHP:
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.ALL;
use ieee.std_logic_unsigned.ALL;
entity test_add4_gen is
end test_add4_gen;
architecture test of test_add4_gen is
component adder is
port ( A : in std_logic_vector(2 downto 0);
B : in std_logic_vector(2 downto 0);
Cin : in std_logic;
Sum : out std_logic_vector(2 downto 0);
Cout : out std_logic
);
end component adder;
signal A1 :std_logic_vector( 3 downto 0) :="0110";
signal B1 :std_logic_vector( 3 downto 0) :="0101";
signal Cin : std_logic;
signal Sum1 :std_logic_vector(3 downto 0);
signal Cout :std_logic ;
begin
add: component adder
generic map (32)
port map (A, B, Cin, Sum, Cout);
end test;
PHP:
# ** Error: test_add4.vhd(23): (vcom-1027) Number of positional association elements (1) exceeds number of formals (0).
# ** Error: test_add4.vhd(24): (vcom-1136) Unknown identifier "a".
# ** Error: test_add4.vhd(24): (vcom-1136) Unknown identifier "b".
# ** Error: test_add4.vhd(24): (vcom-1136) Unknown identifier "sum".