Help in Digital Converter with VHDL

[YenYu]

Looks like it's kind of hard to implement it on wat u haf show. Because ur MHz is set to a real no. But in VHDL i dont think it is possible to set a real no. Also ur Mhz uses to the extent of .01 , so it might be even harder, only way i could onli set it to is 125000000 for 125MHz and running from 0MHz to 125MHz using (32bits) inputs is even hard...

I've try on sending some inputs to the DATA pins. Looks like it works like this....

DATA<= "01000000000000000000000000000000", --DDS output at 125MHz
"00111101011100001010001111010111" after 100 ns, --DDS output at 120MHz
"00110011001100110011001100110011" after 200 ns, --DDS output at 100MHz
"00101000111101011100001010001111" after 300 ns, --DDS output at 80MHz
"00011110101110000101000111101011" after 450 ns, --DDS output at 60MHz
"00010100011110101110000101000111" after 600 ns, --DDS output at 40MHz
"00001010001111010111000010100011" after 800 ns; --DDS output at 20MHz

The values i get is by using ur equation u haf given me..

PINC = 2^accumulator_bits * desired_frequency / sample_rate

So after simulation, i got the desired frequency i wanted, all tallies. But then, there is no dropping of amplitude sign.. The range is from 0MHz,5MHz,25MHz,45MHz,65Mhz,85MHz and 105MHz. So i think it might be the filter problem? wat do u think?
I suspect the problem lies in my Frequency Config setting in the FIR Complier v1.0

 

[echo47]

VHDL has "real" type just like Verilog. It also has sine and square-root functions. They work fine in test benches, but XST won't synthesize them.

You could specify the frequency values in hex instead of binary, if that's easier for you.

As I explained earlier, your filter's cutoff frequency is so high that you won't see much amplitude variation no matter what frequency you input into the down-converter. You could redesign the filter coefficients, as I did for my example code.

 

[YenYu]

Code:

% Given the FIR filter taps, calculate and plot the frequency response. 
coeff = hex2dec(['001'; 'ff7'; 'ffe'; '014'; 'fff'; 'fd7'; '009'; '04b'; ... 
                 'fe3'; 'f81'; '04a'; '0d5'; 'f50'; 'e6f'; '21c'; '76b'; ... 
                 '76b'; '21c'; 'e6f'; 'f50'; '0d5'; '04a'; 'f81'; 'fe3'; ... 
                 '04b'; '009'; 'fd7'; 'fff'; '014'; 'ffe'; 'ff7'; '001']); 
coeff = coeff - 4096 * (coeff >= 2048); 
[h w] = freqz(coeff);       % frequency response of filter 
f = 250 * w / (2 * pi);     % frequency values 
a = abs(h);                 % gain values 
plot(f, a); grid on; xlim([0 125]); ylim([0 4500]); xlabel('Frequency [MHz]'); ylabel('Gain'); 
set(gca,'XTick',0:10:125,'YTick',0:500:5000,'XMinorGrid','on','YMinorGrid','on');

Hmm, Maybe i'll try changing it to the coefficient within ur code.

This is the Coeff file that i used in my fitler.

 

[echo47]

That old MATLAB code is merely a copy of your coefficients (-3dB cutoff around 125 MHz).
My Verilog code has new coefficients (-3dB cutoff at 100 MHz).

In case you are wondering how my low-pass filter works, see UG073 Figure 4-7 "Symmetric Systolic FIR":
**broken link removed**

 

[YenYu]

Is it possible for u to generated a coeff file with a -3dB at 62MHz?

 

[echo47]

Here are low-pass filter coeffs with -3dB at 62 MHz and sample rate 500 MHz:
005 FFE FF3 FEA FF3 014 03B 044 00D FA3 F48 F62 033 1A3 332 436 436 332 1A3 033 F62 F48 FA3 00D 044 03B 014 FF3 FEA FF3 FFE 005

 

[YenYu]

Oh.... thanks alot pal... wish it could help ^^.

I'm going to try the coefficient.
Hmm, this coe is also generated from MatLab too? Is MatLab a Programming based programs?

 

[echo47]

I used MATLAB's firceqrip() function to do most of the work.

MATLAB is primarily a programming language with a large library of functions and toolboxes:
https://www.mathworks.com/products/matlab/

The name MATLAB means matrix laboratory.

 

[YenYu]

oh... alrite, thx alot!
I'm trying the coe u gave now.

Added after 1 hours 24 minutes:

New Updates:

Alrite here's the problem. Now after i've change the coe file. It looks like there's some where wrong in my Qt2. I doesnt provide any waveform but staying a line at '0'

Here's my print screen of it.

 

[YenYu]

Hey.. hmm u did mention on setting the binarys value into hex would be easier..
But then how do u declare hex in VHDL?

 

[echo47]

I agree qt2 looks flat. I can't guess what broke.

For hex bit string literal, try changing this:
DATA <= "00111101011100001010001111010111";
to this:
DATA <= X"3d70a3d7";

Why is a VHDL guy asking a Verilog guy how to write VHDL?

 

[YenYu]

Sry dude... Because i really haf no idea about using hexal...
I've generated some results.. looks like there's some distortiong or noise... within the wave for... i've attach a "signal.do" file for the wave

I guess it should be noise. It occurs at 3us..

Here's my code for the DATA input:
DATA<= "00111101011100001010001111010111",--DDS output at 120MHz (5MHz)
"00110011001100110011001100110011" after 1000 ns,--DDS output at 100MHz (25MHz)
"00101000111101011100001010001111" after 2000 ns, --DDS output at 80MHz (45MHz)
"00100011110101110000101000111101" after 3000 ns, --DDS output at 70MHz (55MHz)
"00011110101110000101000111101011" after 4000 ns, --DDS output at 65MHz (60MHz)
"00100000110001001001101110100101" after 5000 ns,--DDS output at 64MHz (61MHz)
"00100000010000011000100100110111" after 6000 ns,--DDS output at 63MHz (62MHz)
"00011111101111100111011011001000" after 7000 ns, --DDS output at 62MHz (63MHz)
"00011111001110110110010001011010" after 8000 ns, --DDS output at 61MHz (64MHz)
"00011110101110000101000111101011" after 9000 ns,--DDS output at 60MHz (65MHz)
"00011110001101010011111101111100" after 10000 ns,--DDS output at 59MHz (66MHz)
"00011100001010001111010111000010" after 11000 ns,--DDS output at 55MHz (70MHz)
"00010100011110101110000101000111" after 12000 ns;--DDS output at 40MHz (85MHz)

 

[YenYu]

Updates::

This is werild... looks like something is wrong. It doesnt tally with the COE file. The COE file cut-off is at ard 62MHz, but from the simulation i've seen, the amplitude is reduce at ard 45MHz.

Added after 1 hours 8 minutes:

Hmm... Looks like changing the DDS to the programmable will affect the output of the Qt2. It seems like it's onli giving the output to It2 and not towards Qt2. I verified this by change back the DDS to the fixed mode.

 

[echo47]

I tried changing the DDS to programmable, and it still works fine.

The "do" file simply configures the ModelSim display.

Here's a plot of the filter with 62 MHz -3dB cutoff.

 

[YenYu]

Hmm.... Is this the one u make the COE file for mi?
I'm trying on solving my Qt2, I dont know why it came out a straight line.. It's kinda confusing.

I think the best way is still to solve the Qt2 b4 any proceed. What should be the cause of it?

 

[echo47]

I may be able to help diagnose the dead Qt2 signal if you show me your current code. Please keep it small, only the *.vhd and *.mif files.

Yes, graph3.gif shows these coefficient running at 500 MHz clock:
005 FFE FF3 FEA FF3 014 03B 044 00D FA3 F48 F62 033 1A3 332 436 436 332 1A3 033 F62 F48 FA3 00D 044 03B 014 FF3 FEA FF3 FFE 005

Here's the MATLAB code that generated those coefficients and plot:

% Build a FIR lowpass with 12-bit hex coeffs
fs = 500.0;
fc = 62.0; b = round(4096 * firceqrip(32-1, 2*fc/fs+0.024, [0.002 0.002])); % -3dB at 62 MHz
[H,f] = freqz(b);
plot(f*fs/2/pi, 20*log10(abs(H))); grid on; ylim([0 80]); set(gca,'XMinorGrid','on'); xlabel('Frequency [MHz]'); ylabel('Gain [dB]');
b = bitand(uint32(int32(b)+4096), 4095);
dec2hex(b)

 

[YenYu]

Alrite... here's my code. I've onli include 6 files that u mentioned last time.

 

[YenYu]

Does Fc means Frequency Cut-off?

 

[echo47]

In your new code, the filters are somehow sampling at 250 MHz instead of 500 MHz. Notice that it2 updates every 4ns instead of 2ns. Check your coregen settings.

Yes, fc is cutoff frequency. I had to tweak it manually (the +0.024 value) because firceqrip normally designs the filter for -6dB at cutoff instead of -3dB at cutoff.

 

[YenYu]

From the COREGEN setting , The Clock Freq is at 500MHz,and Sampling Freq at 250MHz. Aint it?

Notice that it2 updates every 4ns instead of 2ns.

HOw do u see? Hmm, i'm not quite sure about this.