Help in Digital Converter with VHDL

[YenYu]

So now my cut off frequency is 2 times the previous we haf calculated? which means its 124MHz?

And the X-axis of the magnitude response graph is 0MHz to 250MHz?

So looks like everything is 2times?

Added after 6 minutes:

I suggest leaving the filter clock at 500 MHz, and changing the filter coefficients so it cuts off around 62 MHz, or wherever you need it.

But how should i change the filter Coefficient?

 

[echo47]

Yes, if you clock a digital filter at double speed, then all of its frequency characteristics will be doubled too.

Probably any FIR filter design program will work, but it's probably easiest to reuse the same program that generated the coefficients you are using now.

 

[YenYu]

Oh... alrite... hmm, now i've to try implementing the DDS with a programmable output frequency. Let's say i've set the output freq to programmable. But there's 2 new input pins which is WE and DATA pins. I'm not too sure on how to use it and wat's the use of it....

I suppose the DATA pin is feeding the data into the DDS rite? (Guessing)

Let's say i wanna send in different frequency over some time, how should i implement or set it?

Added after 43 seconds:

So from this way, i think i should know whether is my filter working correctly or not. =) thx

 

[echo47]

To understand WE and DATA, you should read the core's data sheet.

Your PowerPoint says the sample rate is both 480 MHz and 500 MHz. Which is correct?

The PowerPoint says the bandwidth is 200 MHz. If that's correct, then you should clock the filters at 500 MHz (or 480 MHz?), and adjust their coefficients so they cutoff at 100 MHz. Right now, the filters are so wide that you probably won't see significant roll-off of the output amplitude as you sweep your mixer's RF input from near 0 MHz to near 250 MHz.

 

[YenYu]

In powerpoint , the actual is 480MHz, but right now we are testing with a easier no. at 500MHz. When it's able to work, we would try to implement with 480 MHz.

Alrite, the filter i've tried to clock it at 500MHz.
Sampling frequency i've set to various point. ranging from 10-250MHz.there's some little different.

Does the data pins need to load from some files? or just type coding(VHDL)?

 

[echo47]

DATA and WE are input ports. You connect them to signals in your VHDL code.

 

[YenYu]

Hmm... for DATA description i'm not veri sure...

Time shared data bus. The DATA
port is used for supplying values to
the PINC or POFF registers.

Wat does this mean?

 

[echo47]

PINC (phase increment) and POFF (phase offset) are addressable registers. To write into one of them, you must supply a register address "A", write enable "WE", and your data value "DATA".

 

[YenYu]

Hmm... this is the part... how am i going to know it should load from a look-up table or assign it by myself for the DATA pin.
Like:
DATA<= '1';
DATA<= '2'; and so on...
I guess this should be the wrong way....

So let's say, i wan my Output frequency of the DDS to swing from a certain range over a certain time, how should i set it going throught the DATA pin. I've notice it's a 32bit Input, so it should load from a certain look-up table rite?


WE should be a pin like RDY and RFD, setting it to a logic '1' all the way should be alrite i guess.

 

[echo47]

When you configure the DDS core for programmable frequency, it provides the DATA, WE, and A input ports so your HDL can access the PINC register. If you want to continuously update the PINC register, try connecting A to zero, WE to one, and DATA to your logic that generates a sequence of frequency values.

I haven't tried it. I only read the data sheet.

 

[YenYu]

yep... but on the DATA pin, i'm still kind of unsure...
Because it's using a 32bit input. So, i think it should be using a LUT rather then normal assigning.

It's way too long to assign it normally..

 

[echo47]

32-bit DATA is fine. You use it to write your frequency value into the 32-bit PINC register.

For example, if you want to set the DDS to 130 MHz:
PINC = 2^accumulator_bits * desired_frequency / sample_rate
PINC = 2^32 * 130 MHz / 500 MHz
PINC = 1116691497 (decimal) = 428F5C29 (hex)

 

[YenYu]

Oh... thkx for e equation! But then... how should i assign it? let's say i would like to haf a 130MHz and a 75MHz at a certain time.

 

[echo47]

That sounds like a VHDL coding question. Sorry, I don't know VHDL well.

When is "a certain time?"

 

[YenYu]

Hmm, a little on VHDL i guess...

Let's take an example:

Let's say. I wan to sample some frequency within 1ns.
Take into consideration of the cut-off freq at 62MHz for testing.
Then the output frequency of the DDS, I would like to haf 120MHz for the 1st 100ps, 100MHz for the next 200ps, 75MHz for the next 500ps, and 50Mhz for the rest of 200ns.

From the output i should see different frequency waveform at different timing. And also the amplitude dropping after the cut-off frequency.

This is about an idea of the rest of my project. This example should be an ez way of proofing whether my down-converter is working or not.

So, I wanted to know. how should i assign those frequency i wanted to the DATA pins? Should it be like this :

An example. 32bit is too long to count, so i put it in short.

DATA<= "000000000000000000000" after 100ps,"00000000010100100000" after 200ps, .....

It's the part where how do u assign a 32bit into ur DATA pin. Using LUT? or the example i've shown? or maybe some other ways?.

32-bit DATA is fine. You use it to write your frequency value into the 32-bit PINC register.

How should i do it?

 

[echo47]

I guess you need to ask someone else. It's probably only a few lines of code, but I don't know VHDL. I only know Verilog.

You don't want "ps". That means picoseconds, an extremely small value.

 

[YenYu]

Hmm... do u think it is possible to find a free Verilog to VHDL converter websites around? If it is... it could help alot.

Perhaps u could write a part where u assign in verilog? cos maybe i could see from there.

 

[echo47]

Free Verilog to VHDL converter? Even the commercial ones are just awful, IMHO.

Maybe this Verilog stuff will give you some ideas. The testbench generates a 50 microsecond frequency sweep from 0 MHz to 250 MHz (signal rf_in). The "top" module contains the oscillator/mixer and two low-pass filters (-3dB at 100 MHz). The testbench also calculates and displays the filter output amplitude. I positioned the cursor near the filter's -3dB point.

module testbench;
  parameter                 period = 2.0;    // clock period, nanoseconds
  reg                       clk = 0;
  real                      phase = 0.0, MHz = 0.0;
  reg signed          [9:0] dds = 0;
  wire signed        [26:0] i_out, q_out;
  reg signed         [26:0] amplitude;

  always #(period / 2) clk = ~clk;

  top top (.clk(clk), .rf_in(dds), .i_out(i_out), .q_out(q_out));

  always @ (posedge clk) begin
    dds <= 511 * $sin(phase);
    phase <= phase + 2 * 3.1415926535 * MHz * period / 1000;
    MHz <= MHz + 0.01;
    amplitude <= $sqrt(1.0 * i_out * i_out + 1.0 * q_out * q_out);
  end
endmodule


module top (clk, rf_in, i_out, q_out);
  integer                   n;
  input                     clk;
  input signed        [9:0] rf_in;
  reg                 [1:0] t = 0;
  reg signed          [9:0] idelay [0:31], qdelay [0:31];
  reg signed         [10:0] iadd [0:15], qadd [0:15];
  reg signed         [10:0] iadda [0:15], qadda [0:15];
  reg signed         [10:0] iaddb [0:15], qaddb [0:15];
  reg signed         [11:0] coeff [0:15];
  reg signed         [26:0] imul [0:15], qmul [0:15];
  reg signed         [26:0] isum [0:15], qsum [0:15];
  output reg signed  [26:0] i_out, q_out;

  initial begin
    // low-pass filter coefficients (-3dB at 100 MHz when fs=500 MHz)
    coeff[ 0]=12'h00A; coeff[ 1]=12'h006; coeff[ 2]=12'hFEF; coeff[ 3]=12'hFEA;
    coeff[ 4]=12'h010; coeff[ 5]=12'h034; coeff[ 6]=12'h004; coeff[ 7]=12'hFAC;
    coeff[ 8]=12'hFC5; coeff[ 9]=12'h068; coeff[10]=12'h0A2; coeff[11]=12'hFB6;
    coeff[12]=12'hEAC; coeff[13]=12'hFA6; coeff[14]=12'h30C; coeff[15]=12'h645;
  end

  always @ (posedge clk) begin
    // quadrature mixer
    t <= t + 1;
    idelay[0] <= (t == 0) ? rf_in : (t == 2) ? -rf_in : 0;
    qdelay[0] <= (t == 1) ? rf_in : (t == 3) ? -rf_in : 0;
    // symmetric systolic FIR filter
    for (n=1; n<32; n=n+1) begin
      idelay[n] <= idelay[n-1];
      qdelay[n] <= qdelay[n-1];
    end
    for (n=0; n<16; n=n+1) begin
      iadd[n]  <= idelay[2*n] + idelay[31];
      qadd[n]  <= qdelay[2*n] + qdelay[31];
      iadda[n] <= iadd[n];
      qadda[n] <= qadd[n];
      iaddb[n] <= iadda[n];
      qaddb[n] <= qadda[n];
      imul[n]  <= iaddb[n] * coeff[n];
      qmul[n]  <= qaddb[n] * coeff[n];
      isum[n]  <= imul[n] + (n == 0 ? 0 : isum[n-1]);
      qsum[n]  <= qmul[n] + (n == 0 ? 0 : qsum[n-1]);
    end
    i_out <= isum[15];
    q_out <= qsum[15];
  end
endmodule

 

[YenYu]

always @ (posedge clk) begin
rf_in <= 511 * $sin(phase);
phase <= phase + 2 * 3.1415926535 * MHz * period / 1000;
MHz <= MHz + 0.01;
amplitude <= $sqrt(1.0 * i_out * i_out + 1.0 * q_out * q_out);
end

From ur graph, i've see it looks like it's counting from 0 to 250MHz. But it's still kinda hard to exact out from ur verilogs. I've got some ideas from it.
What does the phase used for?
Is ur rf_in a signal into the DDS? or u are just generating it directly to the input of the filter?

 

[echo47]

You can interpret those four lines exactly like any ordinary programming language.

The first two lines are the DDS. It uses the sine function instead of a sine lookup table. "phase" is the phase accumulator. The DDS output was named "rf_in", but that was a bad name so I changed it to "dds".

The "MHz" statement increases the DDS frequency by 10 kHz per clock tick.