I suggest leaving the filter clock at 500 MHz, and changing the filter coefficients so it cuts off around 62 MHz, or wherever you need it.
Wat does this mean?Time shared data bus. The DATA
port is used for supplying values to
the PINC or POFF registers.
How should i do it?32-bit DATA is fine. You use it to write your frequency value into the 32-bit PINC register.
module testbench;
parameter period = 2.0; // clock period, nanoseconds
reg clk = 0;
real phase = 0.0, MHz = 0.0;
reg signed [9:0] dds = 0;
wire signed [26:0] i_out, q_out;
reg signed [26:0] amplitude;
always #(period / 2) clk = ~clk;
top top (.clk(clk), .rf_in(dds), .i_out(i_out), .q_out(q_out));
always @ (posedge clk) begin
dds <= 511 * $sin(phase);
phase <= phase + 2 * 3.1415926535 * MHz * period / 1000;
MHz <= MHz + 0.01;
amplitude <= $sqrt(1.0 * i_out * i_out + 1.0 * q_out * q_out);
end
endmodule
module top (clk, rf_in, i_out, q_out);
integer n;
input clk;
input signed [9:0] rf_in;
reg [1:0] t = 0;
reg signed [9:0] idelay [0:31], qdelay [0:31];
reg signed [10:0] iadd [0:15], qadd [0:15];
reg signed [10:0] iadda [0:15], qadda [0:15];
reg signed [10:0] iaddb [0:15], qaddb [0:15];
reg signed [11:0] coeff [0:15];
reg signed [26:0] imul [0:15], qmul [0:15];
reg signed [26:0] isum [0:15], qsum [0:15];
output reg signed [26:0] i_out, q_out;
initial begin
// low-pass filter coefficients (-3dB at 100 MHz when fs=500 MHz)
coeff[ 0]=12'h00A; coeff[ 1]=12'h006; coeff[ 2]=12'hFEF; coeff[ 3]=12'hFEA;
coeff[ 4]=12'h010; coeff[ 5]=12'h034; coeff[ 6]=12'h004; coeff[ 7]=12'hFAC;
coeff[ 8]=12'hFC5; coeff[ 9]=12'h068; coeff[10]=12'h0A2; coeff[11]=12'hFB6;
coeff[12]=12'hEAC; coeff[13]=12'hFA6; coeff[14]=12'h30C; coeff[15]=12'h645;
end
always @ (posedge clk) begin
// quadrature mixer
t <= t + 1;
idelay[0] <= (t == 0) ? rf_in : (t == 2) ? -rf_in : 0;
qdelay[0] <= (t == 1) ? rf_in : (t == 3) ? -rf_in : 0;
// symmetric systolic FIR filter
for (n=1; n<32; n=n+1) begin
idelay[n] <= idelay[n-1];
qdelay[n] <= qdelay[n-1];
end
for (n=0; n<16; n=n+1) begin
iadd[n] <= idelay[2*n] + idelay[31];
qadd[n] <= qdelay[2*n] + qdelay[31];
iadda[n] <= iadd[n];
qadda[n] <= qadd[n];
iaddb[n] <= iadda[n];
qaddb[n] <= qadda[n];
imul[n] <= iaddb[n] * coeff[n];
qmul[n] <= qaddb[n] * coeff[n];
isum[n] <= imul[n] + (n == 0 ? 0 : isum[n-1]);
qsum[n] <= qmul[n] + (n == 0 ? 0 : qsum[n-1]);
end
i_out <= isum[15];
q_out <= qsum[15];
end
endmodule
From ur graph, i've see it looks like it's counting from 0 to 250MHz. But it's still kinda hard to exact out from ur verilogs. I've got some ideas from it.always @ (posedge clk) begin
rf_in <= 511 * $sin(phase);
phase <= phase + 2 * 3.1415926535 * MHz * period / 1000;
MHz <= MHz + 0.01;
amplitude <= $sqrt(1.0 * i_out * i_out + 1.0 * q_out * q_out);
end
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