wadaye
Full Member level 4
Hi all:
It's hard to test the a complicated verilog design with only one
testbench. So when I use more than one testbench fils to verify my
design, how can estimate the coverage? Is there some simulation tool or
coverage tool can do this work?
wang1
It's hard to test the a complicated verilog design with only one
testbench. So when I use more than one testbench fils to verify my
design, how can estimate the coverage? Is there some simulation tool or
coverage tool can do this work?
wang1