Help for SRAM layout!

[zwangsv]

sram layout

I am doing a layout for SRAM. Each cell has six transistors. I finished the layout for a single cell. I understand that I can flip the cell in such a way to share the well and diffusion to make the layout more compact.

But the problem, will there be any latchup problem after it is manufactured, since those cells are so close? Do you know if there is any isloation between those cells? Technology we are using TSMC0.3, 5 melts, 1 poly. Thank you very much for your reading this.

 

[Colbhaidh]

cmos sram layout

As long as you do not violate any active to active spacing or un related well to unreleated well spacing, you will have no latch up problems. Go ahead and mirror your CELL X and Y.

 

[Nugget]

layout sram

It is better to add ohm contact on upper level. For example , 64M consists of 4 16M banks . 16M-bank consists of 4 4M-blocks . 4M bolck consists of 16 256k-segments. 256K-segments consists of 256K cells . Maybe you can add ohm contact in segement level .

 

[jordan76]

sram layout design flow

Hi

One more thing:you should add some power strappings to your array,say one strapping every 8 cells. The number of power strapping depends on your specificaiton;trade-offs between speed/power/area are often necessary.

Hope it helps.

regards,
jordan76

 

[fiber7]

cmos sram layout design

Hi.

Is there any documentation on SRAM Memory Design Flow.
I have some books on memory design, but a detailed document on the steps required to close the complete design flow would be very useful.

Regards.

Fib

 

[kwkam]

sram library

You can refer to the SRAM library from TSMC. Usually, you can place psub contact and nsub contact at each of 8 or 16 cell. You can calculate the p-sub current from the EDR

 

[freewing]

sram design cmos

Normally, latch-up happens only in the interface of chip to the outer world. Don't worry latch-up in you case.

 

[ananish]

layout considerations sram

can anybody provide the design considerations for sram layout design

 

[laglead]

sram latch up

Could anyone give some comment on the book "cmos memory circuits" by Haraszti , Tegze P. ?
I am an analog designer, but I am a novice in memory design. Espesially I want to do learn more in DDR memory design. Does this book is useful for me?

 

[vikadik]

sram layout requirements

Check out this book. They have a color layout of 6 transistors SRAm

CMOS VLSI Design
A Circuits and Systems Perspective
(3rd Edition)
Neil Weste and David Harris
Addison Wesley
ISBN: 0-321-14901-7

 

[asktech]

latch up sram layout

Do you have this book in PDF format? If so, please share.

Many thanks,
A.T

 

[alpeshchokshi]

sram, latch up

hey chek out this book for memory design its really nice one.
Analysis and Design of Digital Integrated circuits by
David A. Hodges

whole memory design and its sizing steps are given nicely

 

[dasong]

sram layouts

i have the same problem.who can gave some useful link.

 

[Snoy]

sram latchup problem

I have bought the book "Analysis and Design of Digital Integrated circuits" by David A. Hodges. It's really helpful in the SRAM design.

 

[aria62]

Re: cmos sram layout design

Hi.

Is there any documentation on SRAM Memory Design Flow.
I have some books on memory design, but a detailed document on the steps required to close the complete design flow would be very useful.

Regards.

Fib

hi

this book has a chapter about memory designs and layouts:
"Digital Integrated Circuits: A Design Perspective (2nd Edition) by Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic"

regards