Ms.Friday
Newbie level 3
Hello,
I chose a Sudoku code to implement it under Cyclone II - FPGA
I'm converting this java code to vhdl:
my vhdl code:
when I run it their is problems with the array
plz help me to make it correct
I chose a Sudoku code to implement it under Cyclone II - FPGA
I'm converting this java code to vhdl:
Code Java - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 public static void initializeBoard() { int counter = 0; board = new int[9][9]; allowedSets = new int [9][9]; // Since no moves have been made, any number can go anywhere. // Start the sets out with all possibilities. for(int i = 0; i < 9; i++){ for( int j = 0; j < 9; j++){ allowedSets[i][j] = counter; counter = counter + 9; } } for (int i = 0; i < sudoku_array.length; i++){ sudoku_array[i] = true; } }
my vhdl code:
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 library ieee; use ieee.std_logic_1164.all; type board_ array is array of (0 to 8, 0 to 8) of integer; type allowedSets_array is array of (0 to 9, 0 to 9) of integer; --Board_array is array (0 to 8, 0 to 8) of Byte; --allowedSets_array is array (0 to 8, 0 to 8) of Byte; entity initalizeBoard is port ( clk: in std_logic; Counter: in integer; i: in integer; j: in integer ); end entity; architecture FA of initalizeBoard is board: integer Board_array; allowedSets: integer allowedSets_array; variable a = sudoku_array'LENGTH; begin clock : process (clk) Loop1: for i in 0 to 9 LOOP Loop2: for j in 0 to 9 LOOP allowedSets(i)(j)<=counter; counter<=counter+9; end Loop1; end Loop2; Loop3: for i in i to a LOOP; a(i)<=true; end Loop3; end FA;
when I run it their is problems with the array
plz help me to make it correct