Help fixing problems in the vhdl Sudoku code

[Ms.Friday]

Hello,

I chose a Sudoku code to implement it under Cyclone II - FPGA
I'm converting this java code to vhdl:

---

Code Java - [expand]
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public static void initializeBoard()
    {
                int counter = 0;
                board = new int[9][9];
                allowedSets = new int [9][9];
 
        // Since no moves have been made, any number can go anywhere.
        // Start the sets out with all possibilities.
        for(int i = 0; i < 9; i++){
                    for( int j = 0; j < 9; j++){
                        allowedSets[i][j] = counter;
                        counter = counter + 9;
                    }
                }
 
                for (int i = 0; i < sudoku_array.length; i++){
                        sudoku_array[i] = true;
                    }
 
    }

---

my vhdl code:

---

Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
 
type board_ array is array of (0 to 8, 0 to 8) of integer;
type allowedSets_array is array of (0 to 9, 0 to 9) of integer;
 
--Board_array is array (0 to 8, 0 to 8) of Byte;
--allowedSets_array is array (0 to 8, 0 to 8) of Byte;
 
 
entity initalizeBoard is 
port (
clk: in std_logic;
Counter: in integer;
i: in integer;
j: in integer
);
 
end entity;
 
architecture FA of initalizeBoard is 
 
board: integer Board_array;
allowedSets: integer allowedSets_array;
variable a = sudoku_array'LENGTH;
 
begin 
clock : process (clk) 
Loop1: for i in 0 to 9 LOOP
Loop2: for j in 0 to 9 LOOP
allowedSets(i)(j)<=counter;
counter<=counter+9;
 
end Loop1;
end Loop2;
 
Loop3: for i in i to a LOOP;
a(i)<=true;
 
end Loop3;
 
 
end FA;

---

when I run it their is problems with the array
plz help me to make it correct

 

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Re: Help fixing problems in the vhdl code

Loops are unrolled in VHDL (i.e. they are just a shorthand way of replicating logic). They don't work the same way as loops in software.

You instead have to use an FSM and counters to cycle through the array.

 

[Ms.Friday]

Re: Help fixing problems in the vhdl code

^
So you advice me to do an FSM for the code and from the fsm I write the code , correct?

+ another qs is my array implementation correct?

 

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Re: Help fixing problems in the vhdl code

^
So you advice me to do an FSM for the code and from the fsm I write the code , correct?

+ another qs is my array implementation correct?

What I suggested is to use counters to index the array (row, column) and an FSM to control everything.

I'm not an expert in VHDL but the array doesn't look like it's defined as a 2D array. Take a look at the following discussion on this thread.

 

[Ms.Friday]

Re: Help fixing problems in the vhdl code

^
thanks I'll try and I hope that it will work with me

 

[FvM]

Various detail errors, e.g. wrong array size, wrong loop range, missing type and signal definitions.

I'm not an expert in VHDL but the array doesn't look like it's defined as a 2D array. Take a look at the following discussion on this thread.

2D (as shown) or 1D*1D array definition are both valid options. The difference matters if you want to access complete array rows at once. Single cells can be accessed with both variants. Because you didn't show relevant Sudoko code except for an (almost trivial) initialization part, we don't know if it's relevant for your code.

 

[Ms.Friday]

^
how can I identify the array size
I did this because that what I knew from the internet

+
Im confused do I use vector or no need
cuz its a 1 integer

 

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It should be a 9x9 grid of integers so 0 to 8 in both dimensions with an integer range of 1 to 9

So you want a array and the values in the array you would make a type that only has a range of 1 to 9.

Since sudoku checks both row and columns for every digit I'm not sure having the array built by rows or columns would help as you will have to index through all elements of a row or column to check the array.