help: debugging 64-bit partitioned ALU verilog code

[umairsiddiqui]

i'm assigned debugging gatelevel verilog code of 64-bit parititioned ALU design.
its my first research-based vlsi job and i'm assigned such a task...............
any way, its my first gatelevel debugging...any code hacking and simulation tips
& tricks, papers related to this issue. also suggest papers/books on general
datapath design.................................................................

 

[jackson_peng]

netlist debugging is almost impossible. however, since the ADD has an regular stucture, the following things might be help:
1. identify the stucture, BK, CLA, CS, RIPPLE... it's very crucial, for each of them is bulid on different equations.
2. identify the critical signals, llike Pi, Gi, in BK structure. And maybe u can do it down from CO.
3. partition the netlist into blocks, base on the Critical signals.
after that you can have a structured, block based, ADD.

Anyway, it's very time consuming, try them on the 4 bit adder first to get to familiar.

good luck

 

[umairsiddiqui]

can you/some-one-else suggest book(s) containing extensive treatment of datapath element design...
...some books just address few types of adders, along with multipler and shifters.

:sad: :sad: