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help: adding counter

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saUNT

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hello
please help mw to add a counter that will stop at 10 and here is the exaxt words from the proffesor
" The dispense state turn the dispense signal on to activate a stepper motor that issimulated on the red LEDR lights.Again, state machines are used for this part. Make sure to add a counter to count a number of steps (i.e. 10) before it stops. Otherwise, your vending machine will have a flaw dispensing soda to the whole population of UNT for 35 cents. A real stepper motor is connected to the board through the global IO pin (GPIO "

and here is the code:

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity stepper is
    Port ( dispense,reset,clk : in std_logic;
    Q : out std_logic_vector(3 downto 0));
end stepper;
 
architecture Behavioral of stepper is
type states is (three,six,twelve,nine);
signal current_state,next_state: states;
signal count: integer:=0;
begin
 
P1:process(reset,clk)
begin
    if reset='0' then 
    current_state<=three;
    elsif rising_edge(clk) then
    current_state<=next_state;
end if;
end process;
 
p2:process(current_state, dispense)
begin
    if  dispense='1' then   --check for dispense active
    case current_state is
 
    when three =>
            Q<="0011";
            next_state<=six;
    when six =>
            Q<="0110";
            next_state<=twelve;
    when twelve =>
            Q<="1100";
            next_state<=nine;
    when nine =>
            Q<="1001";
            next_state<=three;
    when others =>
            Q<="0011";
            next_state<=three;
    end case;
    end if;
end process; 
--GPIO(3 downto 0)<=Q;   --send output to the stepper motor hardware
end Behavioral;

 
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You know google usually works pretty good when searching for a simple query like this "bcd counter vhdl code"...the first returned link is: http://en.wikibooks.org/wiki/VHDL_for_FPGA_Design/4-Bit_BCD_Counter_with_Clock_Enable.

Unfortunately it uses the non-IEEE std_logic_arith and std_logic_unsigned packages, which are Synopsys packages. The IEEE package is numeric_std. You will have to modify the types to make it correct for numeric_std, but I'll leave that as an exercise for the student.
 

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