Help about scrolling phone number on the 7 segments.how to write the test bench

[vodepam2]

Hello

I wrote a vhdl code for scrolling phone numbers and i want to test it with the test bench .I don't know how to write a test bench for this code .Can someone helpe me with the test bench please? and check if i used the correct library .this is the code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity shif1_array is
    Port ( clk : in  STD_LOGIC;
           clr : in  STD_LOGIC;
           x : out  STD_LOGIC_VECTOR(15 downto 0));
end shif1_array;

architecture Behavioral of shif1_array is

signal msg_array: STD_LOGIC_VECTOR(0 to 63);
constant PHONE_NUMBER: STD_LOGIC_VECTOR(63 downto 0) :=x"248D656D1490FFFF";

begin

   process(clr,clk)
	
	begin
	   if clr='1' then
		   msg_array <=  PHONE_NUMBER;
		elsif (clk'event and clk ='1')then
		    msg_array (0 to 59)<= msg_array (4 to 63);
          msg_array (60 to 63)<= msg_array (0 to 3);
	   end if;
	end process;
	x <= msg_array (0 to 15);

end Behavioral;

Thank a lot for your help

 

[TrickyDicky]

A testbench should generate all of the inputs to stimulate the design, so in the case here, all you need to generate are clk and clr. In a testbench, you can use all the stuff that everyone tells you is unsynthesisable.

For example: to generate a 50MHZ clock and clr:

signal clk : std_logic := '1';
signal clr : std_logic;

....

clk <= not clk after 10 ns;
clr <= '1', '0' after 30 ns;

And then just connect them to the ports of your design.

 

[vodepam2]

Thanks is working.:-D:-D:-D