Member level 1
I have a design which requires 32bit adders, I have made a 1bit full adder, and used generate statement in verilog to make it 32bit adder. Will grouping these 1bit adders together in Design Compiler help in optimization or should I just leave them as is?
module fulladder(a,b,cin,sum,cout); input a,b,cin; output sum,cout; assign sum = a ^ b ^ cin; assign cout = (a & b) | (a & cin) | (b & cin); endmodule
141.5 KB Views: 3