# [SOLVED]Group 1bit Adders in Design Compiler

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#### keyboardcowboy

##### Member level 1
I have a design which requires 32bit adders, I have made a 1bit full adder, and used generate statement in verilog to make it 32bit adder. Will grouping these 1bit adders together in Design Compiler help in optimization or should I just leave them as is?

Code:
module fulladder(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;

assign sum = a ^ b ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);

endmodule

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#### sharath666

What do you mean by grouping?

#### beeflobill

##### Member level 3
What type of optimization are you hoping to get?

The logic in the fulladder module you created will be optimized to meet the design constraints as well as design compiler can. If you flatten the design hierarchy, then you will be able to have optimization across the module boundaries, but debugging might be more difficult.

I don't think design compiler will recognize that you are doing an addition operation and optimize by choosing an adder architecture that will better meet the design constraints.

#### keyboardcowboy

##### Member level 1
I don't think design compiler will recognize that you are doing an addition operation and optimize by choosing an adder architecture that will better meet the design constraints.
so how can I make design compiler recognize it as an adder, the design is a simple shift/add multiplier

#### beeflobill

##### Member level 3
so how can I make design compiler recognize it as an adder, the design is a simple shift/add multiplier
I'm not a synthesizer expert, but I'd think that putting the addition operation into the code is the only sure way to signal any synthesizer that you intend the addition operation to be performed. Synthesizers (and all cad software) are pretty dumb.

If this is for learning, then what you are doing is fine.

If you just want to add numbers without pedagogical concerns, just let the synthesizer do the work. You don't even need to make an adder module. Just put the addition where you need it.

Code:
   reg [31:0] a, b;
wire [31:0] sum;
assign sum = a + b;
Or

Code:
reg [31:0] sum, a, b;
always @ (posedge clk or negedge reset) begin
if (reset==0)
sum = 32'h0000_0000;
else
sum = a + b;
end
If you have difficult constraints on your design, then you might need to be more creative and explicit in how the adder is defined. In that case your learning exercise would be very helpful.

If you care about the carry bit then maybe you could be more careful and do something like this:
Code:
   reg [31:0] a, b;
wire [32:0] sum;
assign sum = a + b;
Or this:
Code:
   reg [31:0] a, b;
wire [31:0] sum;
wire carry;
assign {carry, sum} = a + b;
Note, I haven't tested any of this.

#### keyboardcowboy

##### Member level 1
The problem is I am not allowed to use "+" operator.

#### beeflobill

##### Member level 3
Well, then I'd say you have pedagogical concerns and not practical concerns.