the mux is generic in size and in width (i.e it can mux buses):
this is the instansiation of the code :
component mux_n_to_1
generic(
SIZE_OF_MUX_INPUTS : integer := 16;
SIZE_OF_BUS : integer := 32
);
port (
mux_input : in std_logic_vector(SIZE_OF_MUX_INPUTS * SIZE_OF_BUS -1 downto 0);
mux_selector : in std_logic_vector(log2roundup(SIZE_OF_MUX_INPUTS) - 1 downto 0);
mux_output : out std_logic_vector(SIZE_OF_BUS -1 downto 0)
);
end component;
m0: mux_n_to_1
generic map(
SIZE_OF_MUX_INPUTS => SIZE_OF_REG_ARRAY,
SIZE_OF_BUS => SIZE_OF_DATA
)
port map(
mux_input => reg_array, --: in std_logic_vector(SIZE_OF_MUX_INPUTS * SIZE_OF_BUS -1 downto 0);
mux_selector => addr, --: in std_logic_vector(log2roundup(SIZE_OF_MUX_INPUTS) - 1 downto 0);
mux_output => dout --: out std_logic_vector(SIZE_OF_BUS -1 downto 0)
);