generic multiplexer with input vector

[manfer]

I want to design the next multiplexer. A truly generate mux where n represents the number of bits of the selection input (sel), while n indicates the number of bits per input. the circuit has 2^n inputs.

How can i solve this problem using generic function

thanks for your answers

 

[shawndaking]

check how i did it :
i also made a demux in similar way and both worked fine :

--------------------------------------------------------------------------
-- a. First I Will Generate The Muxess -- M = SIZE_OF_MUX_INPUTS-1
-- b. i will Connect the inputs to first muxes -- M = SIZE_OF_MUX_INPUTS/2
-- c. i will Connect all muxes inputs a,b to Previous outputs
-- d. output is the last mux product.
--------------------------------------------------------------------------
-- a. generate the muxes
--------------------------------------------------------------------------
L_idx : for i in 0 to SIZE_OF_MUX_INPUTS - 2 generate
Mux(i) <= MUX_a(i) when MUX_SELECTOR_en(i) = '1' else Mux_b(i);
end generate L_idx;
--------------------------------------------------------------------------
-- b. generate the input connections to input stage muxes
--------------------------------------------------------------------------
Li_idx : for i in 0 to SIZE_OF_MUX_INPUTS / 2 - 1 generate
MUX_SELECTOR_en(i) <= mux_selector(0);
--Mux_a(i) <= mux_input_array(2*i);
--Mux_b(i) <= mux_input_array(2*i+1);
Mux_a(SIZE_OF_MUX_INPUTS / 2 - 1 -i) <= mux_input_array(2*i+1);
Mux_b(SIZE_OF_MUX_INPUTS / 2 - 1 -i) <= mux_input_array(2*i);
end generate Li_idx;
--------------------------------------------------------------------------
-- c. generate all the rest of muxes.
--------------------------------------------------------------------------
Lo_idx : for i in log2roundup(SIZE_OF_MUX_INPUTS) - 2 downto 0 generate
lj_idx : for j in 0 to 2**i-1 generate
MUX_SELECTOR_en(SIZE_OF_MUX_INPUTS - 2**(i+1)+j) <= mux_selector(log2roundup(SIZE_OF_MUX_INPUTS)- 2 -i +1);
Mux_a(SIZE_OF_MUX_INPUTS - 2**(i+1)+ j) <= Mux(2*j + SIZE_OF_MUX_INPUTS - 2**(i+2));
Mux_b(SIZE_OF_MUX_INPUTS - 2**(i+1)+ j) <= Mux(2*j + 1 + SIZE_OF_MUX_INPUTS - 2**(i+2)) ;
end generate lj_idx;
end generate Lo_idx;
--------------------------------------------------------------------------
-- d. product send to output
--------------------------------------------------------------------------
mux_output <= Mux(SIZE_OF_MUX_INPUTS - 2);

 

[manfer]

hy shawndaking thanks for your answer, but I think you didn't understand my question. I want to do a implemetation of mux with variable number of inputs but using the function generic but not with the function generated.

If you have somethink like that i'll appreciate your reply

thanks

 

[shawndaking]

the mux is generic in size and in width (i.e it can mux buses):

this is the instansiation of the code :

component mux_n_to_1
generic(
SIZE_OF_MUX_INPUTS : integer := 16;
SIZE_OF_BUS : integer := 32
);
port (
mux_input : in std_logic_vector(SIZE_OF_MUX_INPUTS * SIZE_OF_BUS -1 downto 0);
mux_selector : in std_logic_vector(log2roundup(SIZE_OF_MUX_INPUTS) - 1 downto 0);
mux_output : out std_logic_vector(SIZE_OF_BUS -1 downto 0)
);
end component;





m0: mux_n_to_1
generic map(
SIZE_OF_MUX_INPUTS => SIZE_OF_REG_ARRAY,
SIZE_OF_BUS => SIZE_OF_DATA
)
port map(
mux_input => reg_array, --: in std_logic_vector(SIZE_OF_MUX_INPUTS * SIZE_OF_BUS -1 downto 0);
mux_selector => addr, --: in std_logic_vector(log2roundup(SIZE_OF_MUX_INPUTS) - 1 downto 0);
mux_output => dout --: out std_logic_vector(SIZE_OF_BUS -1 downto 0)
);