param
Member level 2
Hi all,
Can anyone suggest to provide the delay after the cpld is programmed.
My logic has to work after 3 ms once the device is programmed.
Is it good practice to generate the counter for 3 ms, wait for it and then trigger the
design signals or is there any settings in compiler(Quartus II) to provide that delay/poll any programming pin?
thanks in advance
Can anyone suggest to provide the delay after the cpld is programmed.
My logic has to work after 3 ms once the device is programmed.
Is it good practice to generate the counter for 3 ms, wait for it and then trigger the
design signals or is there any settings in compiler(Quartus II) to provide that delay/poll any programming pin?
thanks in advance