Generate initial delay after the device is programmed.

[param]

Hi all,

Can anyone suggest to provide the delay after the cpld is programmed.
My logic has to work after 3 ms once the device is programmed.
Is it good practice to generate the counter for 3 ms, wait for it and then trigger the
design signals or is there any settings in compiler(Quartus II) to provide that delay/poll any programming pin?

thanks in advance

 

[btminzon]

Hey Param, you can design a capacitor or a Resistor/Capacitor to charge/discharge, in 3ms. You can use the curve of capacitor discharge, and see when will reach TTL or CMOS logic '1' or '0' in 3ms. You can provide a resistor also to be faster or slower. Good luck

 

[saikat]

Two possible wayouts from myside,

1. Keep the reset signal asserted for 3ms.
2. Apply clock after 3ms of programming the device.

Both methods are possible if you control the clock and reset signal from a microcontroller/processor.

 

[param]

Hi,
I am not using any external reset.