Can anyone suggest to provide the delay after the cpld is programmed.
My logic has to work after 3 ms once the device is programmed.
Is it good practice to generate the counter for 3 ms, wait for it and then trigger the
design signals or is there any settings in compiler(Quartus II) to provide that delay/poll any programming pin?
Hey Param, you can design a capacitor or a Resistor/Capacitor to charge/discharge, in 3ms. You can use the curve of capacitor discharge, and see when will reach TTL or CMOS logic '1' or '0' in 3ms. You can provide a resistor also to be faster or slower. Good luck