GBW link to convertion time of pipe line ADC

[yefj]

Hello, I need to connect the GBW concept and input output charging time R*C two combine them into total convertion time.

In the system shown bellow We have 3 stages of pipeline ADC where each stage is as shown bellow.I have 3 1.5BIt stages and last bit is comparator that gives LSB.
Rin=50ohm Rwitch=100ohm(switch resistance) and Rout=100ohm C=1pf as shown bellow

I am given GBW=20GHZ of the amplifer in the pipeline stage.
When we sample one input the bit before is proccessed in the next stage.
i need to find the toltal conversion time of the whole pipe line.

I tried to do the following
Each stage is 1.5Bit so the gain is 2 so by the calculation bellow i fout the TAU of the AMPLIFIER input RC and OUTPUT RC.
But i dont know how i connect these 3 elements to finf the total conversion time of the PIPELINE?
I am not sure what is the exact meaning of TAU in the amplifier?
Thanks.

 

[sutapanaki]

Here are some suggestions that may help you. First, two stages are sampling, one is redistributing or vice versa. Second, you never design the circuit such, that switch on resistances define the dynamics of the feedback circuit with the opamp or ota. It is always the dynamics of the amplifier that dominate, because it is much easier to design low Ron for the switches than high gm of the amplifier..
So, when you sample, your time constant is (50+50)*2C.
When you redistribute, your loop gain will have UGBW=10GHz or less and the circuit will settle with tau =1/(2*pi*UGBW) if you don't slew.
You have B bit ADC, and you will have to settle to at least 0.5LSB for Ts/2, which will tell you how many time constants of settling time you need. Once you know the number of time constants, you can estimate what is the min Ts/2 (usually you need to settle to the accuracy for less than Ts/2). This is valid for settling in both the sampling and redistribution phases.

By the way, you can never build an amplifier with UGBW=20GHz.

 

[yefj]

Hello Sutapanaki, from what you said in each stage ,we have input RC out put RC and TAU of the amplifier.
but how the amplifier GBW is linked to the output RC?
.what is the meaning of TAU exacty?
So when we want to calculate the convertion time of a single stage do i need to disregard RC OUT?
i cant imagine how the TAU of the amplifier which was produced purely from GBW parameter fits with the RCin and RC out?
Thanks.

 

[sutapanaki]

You have that 100 Ohm at the output of the amplifier, but it is inside the feedback loop, so its value is very much decreased, at least for the frequency range where the loop gain is greater than 1. So, that resistor doesn't really matter.
TAU is the same as in a simple RC circuit as it is in the amplifier. In a 1st order frequency response, tau is related to the pole of that response. because tau=1/w_pole. When you have an amplifier with feedback, the loop gain crosses 0dB at some UGBW. The closed loop gain of the system has its -3dB frequency at or very close to the UGBW of the loop. The -3dB frequency of the closed loop system defines the tau but in fact practically speaking that is the same as saying that tau is defined by the UGBW of the loop. And tau in this way also plays role in the speed of settling, because you will need certain number of time constants to settle to some accuracy.

 

[yefj]

Hello Sutapanaki , regarding what you said in the end,how do i calculate exactly the speed of settling given the tau of each section and input output RC?

" And tau in this way also plays role in the speed of settling, because you will need certain number of time constants to settle to some accuracy "
Thanks.

 

[sutapanaki]

V(t)=Vfinal(1-exp(-Tclk/tau))

 

[yefj]

So you completly disregard the input RC and output RC of the pipeline stage.

 

[sutapanaki]

Input RC matter when PhiA and PhiC are on.

 

[yefj]

Hello Supatanaki,So assume we have flash ADC before the mux ,its latency is 100nsec,
And my amplifier in the ipe line stage is some TAU
based on what you sait out full convertion time=latency time of a single stage =100nsec+5*TAU

So i assume that my clock if half clock cycle sampling and half clock cycle processing
so my clock is f=1/100nsec+5*TAU ,correct?
and convertion time and latency time of a single stage is the same thing?
Correct?

"because you will need certain number of time constants to settle to some accuracy "

 

[sutapanaki]

If you have a flash it needs to settle and produce data. But also the input sampling network of the MDAC needs to settle. So, the longest of these settling times puts the limit.