Gate that can delay a signal in in it's input by delta

[master_picengineer]

Hi all,
Do you know a gate that can delay a signal in in it's input by delta.
I need the shematic of this gate at transistor level.
Thanks.

 

[iwpia50s]

Delay gate

A string of even number of inverters or a string of buffers will do the trick. Depending on the delay it is best to avoid delay cells because you can loose your pulse if the frequency is fairly high.

 

[Old Nick]

Re: Delay gate

Make the gates of the inverter large, increasing the capacitance and thus charging time and delay.

 

[master_picengineer]

Re: Delay gate

Thanks you all,
@Old Nick,
Is there any reference/material explaining the approach that you proposed.

@ all
Could you elaborate:
What is the difference between a string of inverter and a string of buffer. Have you a shematic.
In fact i used this solution but I couldn't obtain the delay. Please help.

 

[iwpia50s]

Re: Delay gate

There really is no difference other than to keep the signal un-inverted you must use a pair of inverters. The transistor level schematic of an inverter is just a pmos and nmos transistor with the gates connected. So depending on the desired delay you uses different drive strength buffers or inverters and as many as needed. Obviously, if you several nanoseconds of delay then it is better to think about using a flip-flop to just add a clock delay.

Added after 1 minutes:

Sorry...I forgot the image.

 

[iwpia50s]

Delay gate

Your schematic has a race condition because you have two paths from input to output.

 

[ls000rhb]

Delay gate

chains of inverter can delay the signal. delay cell have been common used as standard cell in cell library.

 

[ericyuan]

Re: Delay gate

should control the PMOS/NMOS drive strength.....