Gate level simulation

[wisemonkey]

Hi everyone,
I'm trying to go through vcs tutorial to get an idea of gate level simulation
I already have a synthesized design (on which I worked through last semester)
So now I'm trying to issue (since toshiba libraries have protected tag in them)

vcs +v2k -sverilog top.v tb.v design.postsynth.v -y ./lib/verilog/tc240c +libext+.tsbvlibp

However I still receive an error as bad encryption in one of library file and at token "protected"

Thanks for any suggestions

 

[ljxpjpjljx]

have you read the sdf file?

 

[wisemonkey]

no.
I created netlist(design.postSynth.v) file with help of write (format verilog) command for dc_shell. As of now I do not now the procedure/command to create sdf file.

Thanks

Added after 18 minutes:

Here is a flow that I understood from general reading and my courses: (I'm sure there are parts missing especially after synthesis please correct me)

Design (verilog code writing from specs)
Functional simulation (just design file and testbench)
Synthesis (area/timing reporting use of design library with design file)
Post synthesis simulation (with help of same testbench as in step 1 and netlist file obtained in step 3 and library sources)
Place and Route (I'm yet to explore it however as much I've read: automated process with help of tool and netlist file)

 

[wisemonkey]

hmm can anyone let me know if I'm doing it right way or wrong, so that I can continue reading/searching if I'm wrong.

Thanks for any suggestions

 

[randyest]

Annotating an SDF or not has nothing to do with an error message about encryption. Can you quote the exact error message? I maybe able to help if you can provide the details.

 

[wisemonkey]

Sure here is exact error: (after parsing few files correctly)

Protected code was not created by VCS - cannot decode.

Error-[BE] Bad encryption
Started encryption outside a module or in another scope.
"./lib/verilog/tc240c/tsbMUXXprim.tsbvlibp", 7: token is '`protected
'
`protected
^

 

[randyest]

It looks like your encrypted model was encrypted by a tool other than vcs. Maybe NCVerilog or some FPGA tool? In my experience encryption is tool-specific. Maybe ask your vendor / fab what tool they encrypted it with and see if they can re-do it for vcs? Sorry I can't be of more help.

 

[wisemonkey]

hmm its on my university machine so I'll have to talk to lab administrator.
Thanks for pointing out it

 

[asicganesh]

You can use write_sdf to generate sdf file from your dc_shell itself

 

[randyest]

You can use write_sdf to generate sdf file from your dc_shell itself

Am I missing something? Why do you think SDF annotation has anything to do with an encryption problem?

According to his error message, vcs is saying it can't decrypt a module (some primitive cell.) Even if SDF annotation failed (which we have no evidence of) vcs obviously can't decrypt something. This happens before SDF annotation. Decryption fails. SDF annotation apparently has nothing to do with it. Or am I missing something? Please explain your idea more fully so we can understand.

 

[heartfree]

Agree with randyest.
It should be tools chain issue, please try ncsim.

 

[wisemonkey]

Thanks everyone,
especially randyest.
The library was encrypted with cadence tool (ncverilog) and I didn't have ncverilog by default in my PATH variable.
Anyway that was fixed by editing cshrc, now I can get it to start simulation with ncsim, well I've few errors to tackle though will report in again as I go through gate level simulation
pini thanks but I've used fpga tools for process however this time wanted to follow complete ASIC flow

Added after 39 minutes:

So next question is:
I would suppose it is important to use

flatten and uniquify

if I've modules in other file?

Thats exactly where I'm stuck currently as I can get netlist but I think because I've FIFOs outside design (which I've instantiated in design) I can't simulate it properly
Is that correct? Or is there anything else that I need to check?

 

[wisemonkey]

Hi everyone,
I've a request can anyone post a tutorial for ncverilog - especially focusing on gate level simulation. I've one which I'm currently reading if that solves my issue I'll post.
Plus it would be really great if its not just commands but maybe something explained step by step maybe with some reference design.

Here is situation:
I read 3 files and created netlist for design that looks something like

FIFO -- DESGIN -- FIFO

Each fifo has its own memory but I can't use it in netlist generation (I'm not exactly clear why but as I know memories shouldn't be synthesized) so basically when ncsim starts it presents with error as few ports are not connected and I get simulation error identical to functional simulation error when I had messed up FIFO connections.

I know this information may not be enough to comment on but I would appreciate just a tutorial as well, I'll try to look through.

Thanks

 

[wisemonkey]

Turns out its not issue with tools anymore. I was using ncverilog correctly however now it needs to be debugged at gate level (since Functional verification and synthesis turns out to be correct). And looking at number of signals in post synthesis netlist, its daunting even to think of debug so for now I've stopped working towards place and route which was next in line.