Gate level simulation: check the function on netlist with timing information.
System validatin: Maybe the post silicon test. check the function on real chip.
People use validation & verification to ensure correctness of the SOC .
Both will ensure SOC will function according to Specification .
One in RTL and other in post silicon ...
Gate Level simualtion is to check dynamic behaviour of the ckt as STA check static timing only . Apart from this all assumption STA ( like multy cycle paths,false paths and other clk exceptions ) are verified in GLS .
Hi,
Gate Level Simulations gives violations on any signals which are affected due to synthesis. For example, due to some delays statemachines in RTL may go into X state. From such signals identified from Gatelevel netlist, we need to identify, whether it is due to synthesis constraints or due to bugs in RTL design.
Regards,
ramana