gate level simulation,system validation

[giri_lp]

Hi,
Can anyone brief me about gate level simulation and system validation concepts?

Thanks in advance

 

[Zeng Jie-jun]

Gate level simulation: check the function on netlist with timing information.
System validatin: Maybe the post silicon test. check the function on real chip.

 

[giri_lp]

Hi can any one brief me more about this system validation....

Thanks in advance

 

[yln2k2]

Hi ,

People use validation & verification to ensure correctness of the SOC .
Both will ensure SOC will function according to Specification .
One in RTL and other in post silicon ...

Gate Level simualtion is to check dynamic behaviour of the ckt as STA check static timing only . Apart from this all assumption STA ( like multy cycle paths,false paths and other clk exceptions ) are verified in GLS .


Thank & Regards
yln

 

[au_sun]

SYSTEM VALIDATION: It is validating the functional correctness of the WHOLE system by integrating All the BLOCKs in the system.

 

[satya_422]

How Gate lavel simulation gives voilations, is it on path based or only on gate level

 

[ramana_k22]

Hi,
Gate Level Simulations gives violations on any signals which are affected due to synthesis. For example, due to some delays statemachines in RTL may go into X state. From such signals identified from Gatelevel netlist, we need to identify, whether it is due to synthesis constraints or due to bugs in RTL design.
Regards,
ramana