gate level simulation error

[siva_7517]

$setuphold<hold>( negedge g &&& (sandr == 1)

Hi,

I have a warning statement form ncverilog after doing a gate level simulation. I am not sure what violation is this?


Warning! Timing violation
$setuphold<hold>( negedge G &&& (SandR == 1):1957 NS, posedge D:1957 NS, 1.000 : 1 NS, 0.500 : 500 PS );
File: /tools/Silterra_fe/aci/sc-x/verilog/silterra18.v, line = 23770
Scope: fft16_tb.uut.out_re_reg_9_
Time: 1957 NS


Warning! Timing violation
$setuphold<hold>( negedge G &&& (SandR == 1):1957 NS, posedge D:1957 NS, 1.000 : 1 NS, 0.500 : 500 PS );
File: /tools/Silterra_fe/aci/sc-x/verilog/silterra18.v, line = 23770
Scope: fft16_tb.uut.out_re_reg_10_
Time: 1957 NS

 

[aji_vlsi]

Hi Siva,
I am splitting your report to few quotes to reply in detail:

Warning! Timing violation
$setuphold<hold>

You have a $setuphold checke, and a HOLD violation occurred.

( negedge G &&& (SandR == 1):1957 NS,

Your violating signal and its time of data change (or event occurence).

posedge D:1957 NS,

Reference event, Clock and its time of change.

Clearly clock and data are changing at the same time - 1957 NS

1.000 : 1 NS, 0.500 : 500 PS );

Your timing limits as set by $setuphold check.

File: /tools/Silterra_fe/aci/sc-x/verilog/silterra18.v, line = 23770
Scope: fft16_tb.uut.out_re_reg_9_
Time: 1957 NS

I hope self explanatory

I believe ncvlog documentation has this detail too.

HTH
Ajeetha, CVC
www.noveldv.com

 

[yln2k2]

Hi ,

Ajeetha gave good explanation .
I want to add one comment .

These violations supposed to be represented as Erroror not warning .
please check whether you are using +SDFwarn ( this is a modelsim cmd, may be you are using similar for nc) .


Thanks & Regards
yln

 

[narendra27]

nice explanation...
what does 1.000:1.000 and 0.500:0.500 means/specify

---------- Post added at 13:40 ---------- Previous post was at 13:38 ----------

Hi Siva,
I am splitting your report to few quotes to reply in detail:




You have a $setuphold checke, and a HOLD violation occurred.



Your violating signal and its time of data change (or event occurence).



Reference event, Clock and its time of change.

Clearly clock and data are changing at the same time - 1957 NS



Your timing limits as set by $setuphold check.



I hope self explanatory

I believe ncvlog documentation has this detail too.

HTH
Ajeetha, CVC
Welcome to CVC

nice explanation...
what does 1.000:1.000 and 0.500:0.500 means/specify

 

[ken811125]

when i do post-route simulation,i got a timing error...

Warning! Timing violation
$setuphold<hold>( posedge CK &&& (flag == 1):4132 NS, posedge D:4132 NS, 1.000 : 1 NS, 0.500 : 500 PS );
File: /usr/cad/ENV/CBDK_TSMC018_Arm_v4.0/CIC/Verilog/tsmc18.v, line = 6398
Scope: tb.Top_pad.Top.AME.PE_1D.PE0B.PSADout_reg_7_
Time: 4132 NS

i don't know how can i debug