Originally By:
bassman59
Expert Contributor
Ah, yet another reason why one shouldn't try to do this in an FPGA ...
When you do a functional simulation, by definition you do not have specific timing information. All gate delays are reduced to what are called delta delays, which are basically infinitesmal. So when you simulate a chain of buffers without explicit delay values (transport, inertial, etc, read your VHDL book) the output of the last buffer will appear to change instantly after the input to the first buffer changes. (What really happens is this: say you have three buffers in series. When the input to buffer 1 changes, its output, and hence the input to buffer 2, changes a delta delay later. Then the output of buffer 2 changes a delta delay later, then the output of buffer 3 changes another delta delay later. This is important for simulation scheduling and can really baffle the unwary in certain cases, but the end result is that it looks as if buffer 3's output changes immediately with buffer 1's input.)
The newbie will then go, "well, I'll just add a delay to each of the buffer assignments," and of course that fails, because that delay, especially in an FPGA, is unknown and varies with voltage, temperature, placement and routing of components within the FPGA, etc. Note well that delays in assignments are ignored by the synthesis tool (how does the synthesis tool know how to create a 1 ns delay?) so your simulation will never match the synthesized reality.
So all of this is to say why we don't do this in FPGA ...