Gate Delay dependent circuits

[ahmedkhalaf]

fpga gate delay

Hi,

I'm trying to implement a ring oscillator using series of inverters, and I need to study the smallest changes in time, but no use with the ISE simulator:

I get the signals changed in the same instant of time.
(I'm using Free ISE 10.1 WebPack)

also I tried a series of buffers and I get all signals changed at the same moment

is there a way to study this?


Thanks

 

[FvM]

gate delay verilog

With recent FPGA families, you can expect 0.3 to 0.5 ns per logic cell. Does the ISE simulator support timing simulation? Did you select timing or functional simulation?

As another remark, the synthesis tool is supposed to remove superfluous logic cells in synthesis. Did you verify in the fitter result, that the intended logic cells have been actually synthesized for the simulated design? You may need to specify special synthesis attributes to keep the logic cells.

 

[ahmedkhalaf]

gate delays in verilog

Thank you FvM...

I dont know if ISE Simulator can do it

I checked the synth. output ... I can get the output I want with some configuration, but I still dont know how to simulate that accurate timing.


Thanks again

Added after 7 minutes:

I have posted the same question on Xilinx Forms... and that what i got :

Originally By:
bassman59
Expert Contributor

Ah, yet another reason why one shouldn't try to do this in an FPGA ...

When you do a functional simulation, by definition you do not have specific timing information. All gate delays are reduced to what are called delta delays, which are basically infinitesmal. So when you simulate a chain of buffers without explicit delay values (transport, inertial, etc, read your VHDL book) the output of the last buffer will appear to change instantly after the input to the first buffer changes. (What really happens is this: say you have three buffers in series. When the input to buffer 1 changes, its output, and hence the input to buffer 2, changes a delta delay later. Then the output of buffer 2 changes a delta delay later, then the output of buffer 3 changes another delta delay later. This is important for simulation scheduling and can really baffle the unwary in certain cases, but the end result is that it looks as if buffer 3's output changes immediately with buffer 1's input.)



The newbie will then go, "well, I'll just add a delay to each of the buffer assignments," and of course that fails, because that delay, especially in an FPGA, is unknown and varies with voltage, temperature, placement and routing of components within the FPGA, etc. Note well that delays in assignments are ignored by the synthesis tool (how does the synthesis tool know how to create a 1 ns delay?) so your simulation will never match the synthesized reality.


So all of this is to say why we don't do this in FPGA ...

Original Thread

Added after 9 minutes:

can you suggest a tool / enviroment that is capable of doing it? ... I'm thinking of Orcad circuit simulation

but I think I need another tool that is more digital circuit oriented

also what about skipping simulation, and testing in the physical circuit ?

 

[omara007]

gate delay fpga

Are you simulating the RTL or the Synthesized Netlist ? .. if this is not acheivable with ISE, then in case you have access to any ASIC compiler (like Synopsys DC, or Cadence RTL Compiler), you will be able to get a netlist that includes gate-delays (which corresponds to cell delays after FPGA synthesis). Then you can simulate the netlist using any RTL simulator like ModelSim or NCSim.

 

[FvM]

vhdl buffer delay ise

The question is answered in the first line of ISim "Getting started".

Xilinx® ISim is a Hardware Description Language (HDL) simulator that enables you to perform functional and timing simulations for VHDL, Verilog and mixed VHDL/Verilog designs.

I expect, the manual has also some more details on timing simulation.

 

[ahmedkhalaf]

xilinx isim transport delay

Thanks FvM and omara007

I'll do some more research and get back with more questions

 

[omara007]

verilog gate delay line

The question is answered in the first line of ISim "Getting started".

Xilinx® ISim is a Hardware Description Language (HDL) simulator that enables you to perform functional and timing simulations for VHDL, Verilog and mixed VHDL/Verilog designs.

I expect, the manual has also some more details on timing simulation.

In general, you can't do any timing simulation before synthesizing your RTL , at least, to Netlist .. the first timing information appears after synthesis .. then more detailed timings appear by going deeper in the backend flow.