Propagation delay

[Mysterion]

Hello everyone

I need to modify the XOR operations used in the parity calculation in such a way that the XOR gates described are each supplemented by a hold time and the propagation delay and use the circuit diagram as a guide.

For the duration of the hold time, the signal used should be assigned the value "X" (invalid) in the VHDL description, and after the delay time, the new valid signal value. Note that signal delays are non-synthesisable constructs.
I'm just confused about the delay implementation. Should X(0)/X(1) be stable for 5ns or 8ns ? and X(2) for 3ns or 5ns ?

That's the code I wrote, but like I said, I'm not sure about the delay implementation and would appreciate some guidance.

library ieee;
use ieee.std_logic_1164.all;

entity parity_gen is
   port( x : in std_logic_vector (2 downto 0);
         y : out std_logic_vector (3 downto 0)
         );
end parity_gen;

architecture sig_handling of parity_gen is
   signal peven: std_logic;
 
    begin
    
   process(peven, x)
        begin
      peven  <= x(0) xor x(1) xor x(2) after 10 ns;
      if  (x(0)'stable(8 ns) and x(1)'stable(8 ns) and x(2)'stable(3 ns)) then
         y  <= peven & x ;
      else
         y  <= 'X' & x after 10 ns;
      end if;
    end process;
end sig_handling;

Thank you in advance for your help !

 

[kaz1]

My view:
Assume zero time as t=0
I expect C will be 'X' until t = 3 but available at t = 8 (3+5)
y will be 'X' until C arrives but at t = 8+3(11) and available at t = 8+3+5(16)

 

[barry]

It's not clear what you're trying to accomplish here. First of all, I've never seen 'hold time' associated with a non-clocked process. Maybe you mean something else?

And, why is there a hold time associated with signal "c"? Drawing a timing diagram might help. The way I see it:

At t=3, x0 and x1 transition from X to valid. At t=8 c=>valid. At t=13, y=>valid.

 

[kaz1]

It's not clear what you're trying to accomplish here. First of all, I've never seen 'hold time' associated with a non-clocked process. Maybe you mean something else?

And, why is there a hold time associated with signal "c"? Drawing a timing diagram might help. The way I see it:

At t=3, x0 and x1 transition from X to valid. At t=8 c=>valid. At t=13, y=>valid.

I think it is about VHDL as the legacy modelling descriptive language when it was founded in the first place before its transition to synthesis subset. A sort of Uni stuff.