module dac (DACout, DACin, Clk, Reset);
output DACout;
reg DACout;
input [ 'MSBI :0] DACin;
input Clk;
input Reset;
for this part , i suggest u do it at ur main...
ur input should be DACin,Clk,Reset
ur output should be DACout
from the verilog code...
Also try to seperate ur main program and testbench nicely so that it wouldnt feel very messy and confusing... when i start my project that time... every pins is everywhere... which main it veri messy...
For example.... u wan to Make ur main input and output.... for ur DAC
Example...
Ur Main Program
-------------------------------------------------------------------------------------------
<architecture>
declare ur main Input & Outputs : 1 / 0 (10 downto 0)<--- if u need this part
<body>
the functions of ur DAC
<end>
-------------------------------------------------------------------------------------------
This should be ur main program... so if it works with ur aspects... never ever touch it unless u need to edit the pins of it.
Then after which, u should do ur TestBench if ur're asked to.
Ur TestBench
-------------------------------------------------------------------------------------------
<architecture>
<component>
define and list out all ur component input & outputs.
<Body>
declare the signals to ur input and output pins of ur component.
functions of read/ write if there is any....
<end>
--------------------------------------------------------------------------------------
this is almost about the whole idea of how u should do it nicely...
try not to put input and output pins every where.... it will make ur crazy confusing.
put notes like...
//DAC 1
--------------
blah blah blah <--- this is which pin? master/self
--------------
//DAC 2
----------------
blah blah blah <---- wat this function does... clock rate? mHz? and stuff like that
----------------
end;
liddat would be more easy to refer and to troubleshoot when there ur fault and error.
Good luck dude.... I'll help u more if there's any problem....
u can add mi
killeryen@hotmail.com =)
Been busy this few days.