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FYP Project help . simple de

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kun

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ad9760 fpga

Hi everyone name is Kun Kun

i ask to use DDS ( core_gen ) to send a wave signal to DAC then come out with Angalog
using this IC Chip

i already got my DDS ( core_gen )

but i don know whats next


is to write a DAC or ??

but if is writing about DAC
what should i take note from the data sheet ( Ic 9760 ARU )
 

echo47

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ad9760 project

I assume you are using some type of FPGA.

I think you mean the Analog Devices AD9760 DAC:
https://www.analog.com/en/prod/0,2877,AD9760,00.html

On your project PC board, you could connect the DAC's data and clock pins directly to your FPGA. Then you write some simple HDL that routes your FPGA clock and DDS data signals to those eleven pins. Depending on signed/unsigned issues, you may need to invert the most significant bit. Be sure your clock/data output timing satisfies the DAC's input setup and hold requirements. You may also need to configure the FPGA output buffer current and slew rate for reasonable rise/fall time and low ringing, as viewed on an oscilloscope.
 

    kun

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kun

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^^ thank you

i do have a pc board which i got to try out later after i complete writing a VHDL and i got to try out on the ic chips
and the out come got to show a Analog signal at the oscilloscope

you mean for now i got to write a simple coding for the clock ??
 

YenYu

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Yo dude... u from nyp? your project looks like my previous project... hehe..

I dont think there's a need to write the clock... u can just prolly edit from the coreGEN but from previous experience, using coreGEN isnt a good way. echo47 did also mention it before during my FYP.
 

    kun

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echo47

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The AD9760 data sheet says the clock/data setup and hold times are 2.0ns and 1.5ns, so be sure that your FPGA output design satisfies those requirements. If you don't consider the timing, the DAC may malfunction, especially if you are clocking it at 125 MHz.

How to achieve that timing at a fast clock rate depends on which type of FPGA you are using. If it's a modern Xilinx FPGA, I would probably use IOB flops for the data outputs, and an IOB dual data rate (DDR) flop for the clock output. That's a good way to get predictable timing between clock and data output pins.
 

    kun

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kun

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thanks you guys for replying me

muahaha never know i get to hear from yenyu at here
YenYu
can you add me in your hotmail
Hey_56@hotmail.com

yup yup
im from nyp
i seem your report.
you work on DDS
. got an "A" for FYP ?

mine is DAC

i really need some guild for you guys out there

err you mention something about the coreGEN
i do have one simple
the wave like .... ( not as nice as yours ) ^^


anyone out there . guild me abit !!
 

YenYu

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Prolly u used the LUT that the coreGEN haf generated.(guessing)

DAC stands for Digital-Analogue Converter?
Which coreGEN did u use?

Wat's the purpose of it? maybe gif mi the whole story? i could help a'lil.

Btw, i get a B+ onli... i guess veri few ppl or not even 1 get A unless u did go for director's presentation
 

    kun

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kun

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but you did well ^^ on your project
are you in NYP now
still schooling right ^^

mine
i need to create a Core_Gen sending it to DAC and come out with Analog signal
for the chips im using is 9760 ARU
thats all
Mr Lai say at the end i need to download to a device and get a wave on the oscillator

thats all part 1 .


part 2

change ADC to Digital
if i can get part 1 . part 2 should be easy ^^
 

YenYu

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So which coregen u using ? i mean like DSS,multiplexer & etc? which do u use?

DAC? u made a program urself(soruce code)?
 

    kun

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kun

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err do you have a simple sin wave Core gem

send it to me hao ma ( really thanksss )

the one i come out with is really very very simple

wanted to see how is like .. a wave, i went to try out your project ( but got error )
don you mind sending it to me

i really want :cry:

really need a hand

you can send me and add me ( hey_56@hotmail.com )
 

YenYu

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If i would to do at home, u wont be able to use it in sch. Mine is a updated version Xilinx 9.1i. I've tried b4 .... u wont be able to load it with Xilinx 8.2g. Also i dont think there is error for my project b4 i left unless some one else edited it making it not to work. If u see, in my project, i dont type out and source code for the sin wave... basically using the CoreGEN , Direct Digital Synthesizer, which generate the sin wave out. And going throught my program, down converter, which give out another waveform and passing throught the low pass filter giving the sine wave.
 

    kun

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kun

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i got it .
i got my CoreGen
now i got to write a COding at DAC
and combin them together and come out with a signal wave ^^

i working on DAC coding

anyone this is in Verilog Module
please help me coverter this to VHDL
i really need help on this
please~



module dac (DACout, DACin, Clk, Reset);
output DACout;
reg DACout;
input [ 'MSBI :0] DACin;
input Clk;
input Reset;

reg ['MSBI+2:0] DeltaAdder;
reg ['MSBI+2:0] SigmaAdder;
reg ['MSBI+2:0] SigmaLatch;
reg ['MSBI+2:0] DeltaB;

always @(SigmaLatch) DeltaB = {SigmaLatch['MSBI+2], SigmaLatch['MSBI+2]} << ('MSBI+1);
always @(DACin or DeltaB) DelTaAdder = DACin + DEltaB;
always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch;
always @(posedge Clk or posedge Reset)
begin
if(Reset)
begin
SigmaLatch <= #1 1'b1 << ('MSBI+1);
DACout <= #1 1'b0;
end
else
begin
SigmaLatch <== #1 SigmaAdder;
DACout <= # SigmaLatch['MSBI+2];
end
end
endmodule
 

YenYu

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Oh... There's no way u can convert that Verilog to VHDL, unless u are veri strong at both language... else the onli way to convert is to buy a software which will convert the verilog to VHDL. Well, the software aint a cheap one and it is not ez to find.

I suggest u get the idea of the coding that u wan to do and start from basic.. as it is not ez to convert directly from ur verilog module.
 

    kun

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kun

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^^ means that i got to start working on the coding myself tmr keke
but can you tell me . what should i take notic .
i got my dadtsheet keke
tell me what to do for start
coding i work my way keke

thankss ^^
 

YenYu

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module dac (DACout, DACin, Clk, Reset);
output DACout;
reg DACout;
input [ 'MSBI :0] DACin;
input Clk;
input Reset;

for this part , i suggest u do it at ur main...
ur input should be DACin,Clk,Reset
ur output should be DACout
from the verilog code...

Also try to seperate ur main program and testbench nicely so that it wouldnt feel very messy and confusing... when i start my project that time... every pins is everywhere... which main it veri messy...

For example.... u wan to Make ur main input and output.... for ur DAC
Example...

Ur Main Program
-------------------------------------------------------------------------------------------
<architecture>
declare ur main Input & Outputs : 1 / 0 (10 downto 0)<--- if u need this part

<body>
the functions of ur DAC

<end>
-------------------------------------------------------------------------------------------

This should be ur main program... so if it works with ur aspects... never ever touch it unless u need to edit the pins of it.

Then after which, u should do ur TestBench if ur're asked to.

Ur TestBench
-------------------------------------------------------------------------------------------
<architecture>

<component>
define and list out all ur component input & outputs.

<Body>
declare the signals to ur input and output pins of ur component.

functions of read/ write if there is any....

<end>
--------------------------------------------------------------------------------------
this is almost about the whole idea of how u should do it nicely...
try not to put input and output pins every where.... it will make ur crazy confusing.
put notes like...



//DAC 1
--------------
blah blah blah <--- this is which pin? master/self
--------------


//DAC 2
----------------
blah blah blah <---- wat this function does... clock rate? mHz? and stuff like that
----------------

end;

liddat would be more easy to refer and to troubleshoot when there ur fault and error.

Good luck dude.... I'll help u more if there's any problem....
u can add mi killeryen@hotmail.com =)
Been busy this few days.
 

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