vikas_lakhanpal27
Member level 1
asic sanity checks
Guys,
I have a question. Assume we have a design we have checked its functnality with respect to Spec with the help of RTL simulations. Now we synthesized the design. Then I did functinol Verification to ensure that RTL and netlist both are functnlly same. Timings we have checked with STA. Assume my constraints are proper in STA and FV and there is no doubt about it.
Now the question is What is the need of Gate Level Simulation then?
Note : STA constraints and FV constraints are proper and there is not doubt about it.
Guys,
I have a question. Assume we have a design we have checked its functnality with respect to Spec with the help of RTL simulations. Now we synthesized the design. Then I did functinol Verification to ensure that RTL and netlist both are functnlly same. Timings we have checked with STA. Assume my constraints are proper in STA and FV and there is no doubt about it.
Now the question is What is the need of Gate Level Simulation then?
Note : STA constraints and FV constraints are proper and there is not doubt about it.