hi vikas,
by static checks, ie. STA for timing verification and Formal Verification for RTL to netlist consistency, then you are "close" to not doing gate level simuation.
You also would need to check the clock domain crossings to ensure that there are no metastability. This can be done with Structural checking tools like Conformal-CDC (which comes built in with your LEC tool) or Real-Intent Clock Verification tool.
However, most people do gate level simulations as a sanity check to make sure that their designs behave cleanly and experience the pleasure of seeing waveforms and catching any glaring mistakes. Moreover, your formal-FV or STA may be constrained (ie. Scan disabled etc). Gate-level sims may be fully unconstratined depending on what mode you want to test.
However, any subtle bugs that FV (formal verification) or STA catches are virtually impossible to identify with gate-level sims.
-- ay