in the code above i don't understand theses syntax:
assign sum5=D2 + {D2[23],D2[23:1]};
assign sum6={D1[22:0],D1[0]} + {D3[23],D3[23:1]} +sum5;
assign sum7=sum6[23:19] + 1'b1;
can you please explain me the meaning
Thks a lot
noura
Thank you Mr. LB for your response. Really i dont undertsatnd. if i want for example sum5=0.5*D2 how can be the syntax in verilog code.
thks a lot
Noura
Thank you Mr. LB for your response. Really i dont undertsatnd. if i want for example sum5=0.5*D2 how can be the syntax in verilog code.
thks a lot
Noura
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity md is
port (
clk : in std_logic;
rst : in std_logic;
k_in : in std_logic_vector(23 downto 0);
v_out : out std_logic_vector(3 downto 0);
v_out_offset : out std_logic_vector(3 downto 0));
end md;
architecture behave of md is
signal D1, D2, D3: std_logic_vector(23 downto 0);
signal sum1, sum2, sum3, sum4, sum5, sum6, sum7, v_fd, v_fd_neg : std_logic_vector(23 downto 0);
begin -- behave
sum1 <= k_in + v_fd_neg;
sum2 <= sum1 + D1;
sum3 <= D1 + D2;
sum4 <= D2 + D3;
sum5 <= D2 + (D2(23) & D2(23 downto 1));
sum6 <= (D1(22 downto 0) & D1(0)) + (D3(23) & D3(23 downto 1)) + sum5;
sum7 <= ("0000000000000000000" & sum6(23 downto 19)) + 1;
process (clk, rst)
begin -- process
if rst = '1' then -- asynchronous reset (active high)
D1 <= (others => '0');
D2 <= (others => '0');
D3 <= (others => '0');
v_out <= (others => '0');
v_out_offset <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
D1 <= sum2;
D2 <= sum3;
D3 <= sum4;
v_out <= sum7(4 downto 1);
v_out_offset <= sum7(4 downto 1)+ "1000";
end if;
end process;
v_fd <= ("00000000000000000000" & not(sum7(4 downto 1))) + 1;
v_fd_neg <= v_fd(3 downto 0) & "00000000000000000000";
end behave;
Here it goes .....
Code:library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity md is port ( clk : in std_logic; rst : in std_logic; k_in : in std_logic_vector(23 downto 0); v_out : out std_logic_vector(3 downto 0); v_out_offset : out std_logic_vector(3 downto 0)); end md; architecture behave of md is signal D1, D2, D3: std_logic_vector(23 downto 0); signal sum1, sum2, sum3, sum4, sum5, sum6, sum7, v_fd, v_fd_neg : std_logic_vector(23 downto 0); begin -- behave sum1 <= k_in + v_fd_neg; sum2 <= sum1 + D1; sum3 <= D1 + D2; sum4 <= D2 + D3; sum5 <= D2 + (D2(23) & D2(23 downto 1)); sum6 <= (D1(22 downto 0) & D1(0)) + (D3(23) & D3(23 downto 1)) + sum5; sum7 <= ("0000000000000000000" & sum6(23 downto 19)) + 1; process (clk, rst) begin -- process if rst = '1' then -- asynchronous reset (active high) D1 <= (others => '0'); D2 <= (others => '0'); D3 <= (others => '0'); v_out <= (others => '0'); v_out_offset <= (others => '0'); elsif clk'event and clk = '1' then -- rising clock edge D1 <= sum2; D2 <= sum3; D3 <= sum4; v_out <= sum7(4 downto 1); v_out_offset <= sum7(4 downto 1)+ "1000"; end if; end process; v_fd <= ("00000000000000000000" & not(sum7(4 downto 1))) + 1; v_fd_neg <= v_fd(3 downto 0) & "00000000000000000000"; end behave;
One possible not practical crude solution will be to use look-up table memory for each multiplication!
Second approach will be use floating point /fixed point multiplier IP.
Third approach use soft-core CPU and do the multiplication in software.
Fourth approach simplify the equations as follows
sum6 <= D1*(1.9821) + D2*(1.5040) + D3*(0.4131);
This can be written as
sum6 <= D1*2 + (D2+D2/2) + D3/2; here I am approximating 1.9821 ~2.0 1.5040 ~ 1.5 and 0.4131 ~ 0.5
Hope this helps!
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