noura7
Member level 2

Please how can i change the following verilog code to vhdl code to understand it. I don't know the meaning of the verilog syntax:
module md(clk, rst, k_in, v_out, v_out_offset);
input clk, rst;
input [23:0] k_in;
output [3:0] v_out, v_out_offset;
reg [3:0] v_out,v_out_offset;
reg [23:0] D1, D2, D3;
wire [23:0] sum1, sum2, sum3, sum4, sum5, sum6, sum7, v_fd, v_fd_neg;
assign sum1 = k_in + v_fd_neg;
assign sum2=sum1 + D1;
assign sum3=D1 + D2;
assign sum4=D2 + D3;
assign sum5=D2 + {D2[23],D2[23:1]};
assign sum6={D1[22:0],D1[0]} + {D3[23],D3[23:1]} +sum5;
assign sum7=sum6[23:19] + 1'b1;
always@(posedge clk or posedge rst)
begin
if(rst) D1<=24'h0;
else D1<=sum2;
end
always@(posedge clk or posedge rst)
begin
if(rst) D2<=24'h0;
else D2<=sum3;
end
always@(posedge clk or posedge rst)
begin
if(rst) D3<=24'h0;
else D3<=sum4;
end
always@(posedge clk or posedge rst)
begin
if(rst)
begin
v_out<=4'b0000;
v_out_offset<=4'b1000;
end
else
begin
v_out<=sum7[4:1];
v_out_offset<=sum7[4:1]+ 4'b1000;
end
end
assign v_fd=~sum7[4:1]+1'b1;
assign v_fd_neg={v_fd[3:0],20'h00000};
endmodule
module md(clk, rst, k_in, v_out, v_out_offset);
input clk, rst;
input [23:0] k_in;
output [3:0] v_out, v_out_offset;
reg [3:0] v_out,v_out_offset;
reg [23:0] D1, D2, D3;
wire [23:0] sum1, sum2, sum3, sum4, sum5, sum6, sum7, v_fd, v_fd_neg;
assign sum1 = k_in + v_fd_neg;
assign sum2=sum1 + D1;
assign sum3=D1 + D2;
assign sum4=D2 + D3;
assign sum5=D2 + {D2[23],D2[23:1]};
assign sum6={D1[22:0],D1[0]} + {D3[23],D3[23:1]} +sum5;
assign sum7=sum6[23:19] + 1'b1;
always@(posedge clk or posedge rst)
begin
if(rst) D1<=24'h0;
else D1<=sum2;
end
always@(posedge clk or posedge rst)
begin
if(rst) D2<=24'h0;
else D2<=sum3;
end
always@(posedge clk or posedge rst)
begin
if(rst) D3<=24'h0;
else D3<=sum4;
end
always@(posedge clk or posedge rst)
begin
if(rst)
begin
v_out<=4'b0000;
v_out_offset<=4'b1000;
end
else
begin
v_out<=sum7[4:1];
v_out_offset<=sum7[4:1]+ 4'b1000;
end
end
assign v_fd=~sum7[4:1]+1'b1;
assign v_fd_neg={v_fd[3:0],20'h00000};
endmodule