Hi,
In a PLL first of all it should try to make VCO frequency equal to that of the reference frequency.after that it decrease phase difference to zero. so that PLL locks. if the difference between ref. frequency VCO frequency higher than certain level PLL fails to lock.in this case we need Frequency Detector(FD) .this FD makes two frequencies equal and after that it losses control on loop and give control to PLL.and PLL try to eleminate Phase Diference. and it locks .mostly clock and data recovery(CDR) circuits use this prnciple.
Regards