How to Simulation loop stablity in clock system

[goatmxj666]

Hello,

I designed digital LDO, and this system contolled by clock.

I want to check stability of this system's loop stability.

first, I did transient simulation when the clock is high and low respectively.

then I fixed all DC voltages for the rest of the system except for the node voltage connected to the loop.

after fix the DC voltages, I simulated the stb simulation with cadence for both environments and it didn't work.

How can I check the stability when the system is clocked?

I would be grateful if you could answer this.

 

[Dominik Przyborowski]

For clocked system use periodic analysis - pss, pac, pstb, pnoise, et cetera

 

[crutschow]

want to check stability of this system's loop stability.

Please show a schematic of "this system".