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Frequency Divider in VHDL

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vlsi_freak

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vhdl frequency divider

Hi.

I am trying to divide a clock by 2, and have the VHDL code is given below.
Now the clock here is divided by 4,,OOOppsss.

How can i write a VHDL code to divide the frequency by 2.

Thanks.


entity freq_div is
port (
clk, rst, d : inout std_logic;
q, qbar : inout std_logic
);
end freq_div;


architecture freq_div_a of freq_div is

begin

process(clk, rst)

begin
if (clk'event and clk='1') then
if rst ='1' then
q <= '0';
qbar <= '1';
d <= '0';
else

q <= d;
qbar <= not d;
d <= qbar;

end if;

end if;

end process;
end freq_div_a;

Please share your ideas.

Thanks
 

vlsi_whiz

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vhdl code for frequency divider

To divide-by 2 just use a D-FF with the Q-bar output tied back to the D input..
This is the basic divide by 2 ckt.. it works..
 
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laststep

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frequency divider vhdl

by right, ur coding should divide the clk by 2. I cant see any wrong form ur coding. Are u sure it divide the clk by 4?
 

kanagavel_docs

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vhdl clock divider

Hi,

In your code each statement will implement as a FF.

qbar <= not d;
d <= qbar;

These statemets will be implemented as two FFs in series as show in the figure



Regards,
Kanags

Added after 7 minutes:

Hi,

Please replace the buffer with NOT gate.
 
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laststep

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clock divider vhdl

ya kanagavel_docs is right,just realize whats wrong when kanagavel_docs point out the error.
Thats why the clk div by 4 not 2.
 

manasiw2

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vhdl code for clock divider

Is this fine?



entity divbytwo_dff is
port(
din : inout std_logic;
q : inout std_logic;
clk,reset : in std_logic
);
end divbytwo_dff;

architecture a_divbytwo_dff of divbytwo_dff is
begin

process(reset,clk)
begin
din <= not q;
if(reset = '0')then
q <= '0';
elsif (clk'event and clk = '1')then
q <= din;
end if;
end process;
end architecture;
 

LordAli

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Re: vhdl code for clock divider

Delete red parts and you will divide by 2.

Is this fine?



entity divbytwo_dff is
port(
din : inout std_logic;
q : inout std_logic;
clk,reset : in std_logic
);
end divbytwo_dff;

architecture a_divbytwo_dff of divbytwo_dff is
begin

process(reset,clk)
begin
din <= not q; -- delete this line
if(reset = '0')then
q <= '0';
elsif (clk'event and clk = '1')then
q <= din;
end if;
end process;
end architecture;
 
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