# [SOLVED]Fraction-N frequency divider

Status
Not open for further replies.
B

#### bjwlgh

##### Guest fraction frequency divide

Can someone give me some vhdl source code about Fraction-N frequency divider.

#### dainis This one takes 3 flip flops and two two-input gates.
The output will have no jitter, provided that the input clock has a
50% duty cycle and the routing delays from the flip flops to the
output gate are matched.

library ieee;
use ieee.std_logic_1164.all;

entity divide1_5 is
port (
gsr : in std_logic;
clk : in std_logic;
divided_clk : out std_logic
);
end entity divide1_5;

architecture rtl of divide1_5 is

signal Q : std_logic_vector(1 downto 0);
signal Q_f : std_logic;

begin

-- divide by 3 counter
divide_by_3 : process (gsr, clk)
begin
if gsr = '1' then
Q <= (others => '0');
elsif rising_edge(clk) then
Q(0) <= not Q(1) or not Q(0);
Q(1) <= Q(0);
end if;
end process divide_by_3;

-- Delay Q1 by half a clock
falling_ff : process (gsr, clk)
begin
if gsr = '1' then
Q_f <= '0';
elsif falling_edge(clk) then
Q_f <= Q(1);
end if;
end process falling_ff;

-- combine the rising and falling edge triggered signals
-- to give an output that has a 1/3 duty cycle, and
-- a frequency of the input clock / 1.5
divided_clk <= Q_f and Q(0);

end architecture rtl;

• Careline

### Careline

Points: 2

#### dainis And other sourse:

B

#### bjwlgh

##### Guest Thank you very much,btw can you give some articles about it.

Thank you very much,btw can you give some articles about it.

#### flowers

##### Member level 1 Hi, bjwlgh:

If you don't care about the output duty cycle isse,
you can try to write a auto-reloaded counter.

flowers

Status
Not open for further replies.