FPGA synthesis timing issue

[layowblue]

Hi all

Our FPGA team is trying to resolve timing issue for my design block.
In 28-nm ASIC, the design meets timing constraint of 500MHz using RC, with sequential to combinational ratio around 1:5.5
While in Virtex7, they used synopsys synthesis tools, and after P&R, timing violation targeting 125MHz reaches -5ns. The FPGA utility is only <50%. Seq:Comb ratio is around 1:30.

This sounds unacceptable to me, since I do not believe current FPGA is so poor at mapping/optimization/P&R. The only thing I know is there is no floor planning in the flow so far to properly inform the tool about block relationships. And there are four SLR regions, some of the signal fans out to multiple SLRs, causing big routing delays.

Could someone shed some light on which FPGA options I should ask the team to check? The team is pretty young, and I don't think they know too much about the most-advanced FPGA tricks.

I don't have much detail information regarding which tool they used for P&R, but I know 24-hours is needed for one syn/P&R round.

Thanks ahead!

 

[ads-ee]

You're missing a lot of details.

Are they using Vivado or ISE flow. Is there a reason they are using synopsys for synthesis? Last time I tested it 2 years ago Synplify Pro (Synopsys FPGA synthesis tool) had worse QoR than ISE XST for a design I was working on. And Vivado has better (and faster) results than ISE for most designs except those that need to use register retiming to meet timing (Vivado doesn't support that feature yet).

What is an SLR? (you should avoid using acronyms on the forum, especially ones that also stand for something else in another unrelated field...do a search for SLR - Single Lens Reflex is the most common usage)

Are the signals that fan out to multiple blocks registered? Even in an ASIC it's a bad practice to send combinational signals to across hierarchical boundaries. If inter block signals are properly registered for both output and input then inter block communication should be running at least 250+ MHz in V7.

24 hours? How big is the design they are implementing? You say it's 50% but how big is that 50%, what V7 part is being used? What kind of system are they running the tools on? i.e. memory/processor/clock_speed. If it's a very large part and they don't have enough memory that will make the P&R very slow as it thrashes the disk swapping memory constantly. Xilinx ISE uses a large amount of memory for the biggest V7 parts.

It's nearly impossible to determine what options to use when you are ending up with an excessive amount of LUT vs. Registers in the design (assuming that is what you mean by Seq:Comb ratio) not much can be done to fix an ASIC design that has enormous logic cones in front of each register, which means many levels of LUTs to implement. Without details I can say that is the problem or not. Maybe the Synopsys synthesis is removing registers that were replicated for fanout.

Regards

 

[jbeniston]

If it's only 500MHz in 28nm, you aint getting 125MHz in an FPGA.

 

[jt_eaton]

Are you using asynchronous resets?

See Xilinx WP231.

 

[layowblue]

Thank you all for the kind reply.
SLR means supper logic region.

I'll collect more information before I update here.

jbeniston, your assertion of 500MHz in ASIC VS 125MHz in FPGA seems a little puzzling to me. Could you elaborate the reasons?

Thanks

 

[rca]

Wel, the Virtex7 family is also in 28nm node as your ASIC and if your ASIC is at the max frequency (500MHz), I could not imagine a fix-glue logic could reach the same timing.

 

[ads-ee]

rca, the OP is trying to meet 125 MHz timing in an FPGA for a 500 MHz timing ASIC. It seems 125 MHz might be an aggressive target for an FPGA given that the ASIC must have very large logic cones between registers to have such a low max frequency.