generating a spread spectrum clock verilog
first - i think that is really hard to implement a spread spectrum oscillator on FPGA. i think that is better that you see at cypress or ti that have spread spectrum generator.
second- if you woud switch when the clock fail i think that you nedd a major frequency, whit this clock you sample the lower clock. whit this philosphy you implement a simple watchdog, when it goes on you switch,
Depending which kind of switcover time you nedd.
bye.
g,