[FPGA] Spread-Spectrum & Clock Switchover (How to ?)

[joe2moon]

fpga spread spectrum

2 question(s) about FPGA technology:

First,
how to implement the spread-spectrum PLL on FPGA ?
/*--- Spread-spectrum clocking schemes
spread the fundamental clock frequency energy
to minimize energy peaks at specific frequencies. ---*/

Second,
how to implement the clock switchover circuity on FPGA ?
/*-- Clock switchover feature can also be used for
switching between clock inputs of different frequencies. ---*/
-------------------------------------------------------------

BTW, can we apply technologies mentioned above to ASIC design ?

ref:
h**p://www.altera.c0m/products/devices/stratix/features/stx-pll_features.html#clock-switchover

 

[tlp71@hotmail.com]

generating a spread spectrum clock verilog

first - i think that is really hard to implement a spread spectrum oscillator on FPGA. i think that is better that you see at cypress or ti that have spread spectrum generator.
second- if you woud switch when the clock fail i think that you nedd a major frequency, whit this clock you sample the lower clock. whit this philosphy you implement a simple watchdog, when it goes on you switch,
Depending which kind of switcover time you nedd.
bye.
g,

 

[joe2moon]

Make my question(s) more clear !

I DO NOT intend to implement
1) spread spectrum PLL, and
2) clock switchover circuity
on FPGA.

What I like to know is "how @ltera implements these on its device ?"

Since I'm wondering if I can use the same technique on ASIC design.

If possible (on ASIC), I would like to know "how to implement them ?"

Furthermore, if them can be done with pure "digital" circuit(s),
then I am interesting about "how to implement them with Verilog ?"