jiang
Advanced Member level 4
FPGA post-sim error
It works fine with Quartus 4.1 + ISU 5.3 on NT platform.
After I update Quartus to version 4.2, FPGA post-sim occurs errors during elabration phase.
The error messages are as follows:
Building instance specific data structures.
ncelab: *internal* (unexpected NT exception -1073741819).
Please contact Cadence Design Systems about this problem
and provide enough information to help us reproduce it.
ncverilog: *E,ELBERR: Error during elaboration (status 1), exiting.
Can anyone help me to fix this problem?
It works fine with Quartus 4.1 + ISU 5.3 on NT platform.
After I update Quartus to version 4.2, FPGA post-sim occurs errors during elabration phase.
The error messages are as follows:
Building instance specific data structures.
ncelab: *internal* (unexpected NT exception -1073741819).
Please contact Cadence Design Systems about this problem
and provide enough information to help us reproduce it.
ncverilog: *E,ELBERR: Error during elaboration (status 1), exiting.
Can anyone help me to fix this problem?