FPGA post-simulation error in Quartus 4.2

[jiang]

FPGA post-sim error

It works fine with Quartus 4.1 + ISU 5.3 on NT platform.
After I update Quartus to version 4.2, FPGA post-sim occurs errors during elabration phase.
The error messages are as follows:
Building instance specific data structures.
ncelab: *internal* (unexpected NT exception -1073741819).
Please contact Cadence Design Systems about this problem
and provide enough information to help us reproduce it.
ncverilog: *E,ELBERR: Error during elaboration (status 1), exiting.

Can anyone help me to fix this problem?

 

[nand_gates]

Re: FPGA post-sim error

Check the diffence in netlist generated by qu@rtus 4.1 and qu@rtus 4.2
May be you will get some clue there!

 

[jiang]

FPGA post-sim error

The simulation model of quartus 4.2 is different from the model of quartus 4.1.
The netlist of quartus 4.2 is different from the netlist of quartus 4.1.

If I don't use SDF, ncsim works.
But ncelab fails when I use SDF.

 

[nand_gates]

Re: FPGA post-sim error

You can try the SDF options available with ncelab
-SDF_CMD_FILE <arg> -- Specifies file of SDF annotation commands
-SDF_NOCHECK_CELLTYPE -- Don't check accuracy of CELLTYPE field
-SDF_NO_WARNINGS -- Do not report SDF warnings
-SDF_PRECISION <arg> -- The precision the SDF data will be modified to
-SDF_VERBOSE -- Include detailed information in SDF log file
-SDF_WORSTCASE_ROUNDING -- For SDF annotation, truncate min delays, round max delays up