FPGA OBUF delay too long

[hithesh123]

I was looking thru the synthesis report of a simple design.
The output buffer delay was listed as 3.2ns. That seems to be too high for a buffer.
Any explanation?

report below -

Timing Detail:
--------------
All values displayed in nanoseconds (ns)


=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 6 / 1
-------------------------------------------------------------------------
Delay: 7.368ns (Levels of Logic = 4)
Source: B<1> (PAD)
Destination: Y2 (PAD)


Data Path: B<1> to Y2
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 1 1.218 0.595 B_1_IBUF (B_1_IBUF)
LUT4:I0->O 1 0.704 0.455 Y21_SW0 (N3)
LUT3:I2->O 1 0.704 0.420 Y21 (Y2_OBUF)
OBUF:I->O 3.272 Y2_OBUF (Y2)
----------------------------------------
Total 7.368ns (5.898ns logic, 1.470ns route)
(80.0% logic, 20.0% route)

 

[joelby]

I think it includes all the time taken to get to the output pin/ball, which is relatively distant compared to things that are on the chip die.

 

[mrflibble]

Sounds about right. It's not so much the delay you have to worry about, but more that the delays for you signals going offchip are equal. Which is the case for IOs in the same bank.

Furthermore ...

Delay: 7.368ns (Levels of Logic = 4)
Source: B<1> (PAD)
Destination: Y2 (PAD)

Are you sure you want 4 levels of logic right before you go to the IO?

Then again, this looks like an async circuit from input pin ==> async logic ==> output pin , so that is probably (hopefully ) on purpose.

Oh and just for the fun of it you can change the drive strength of that Y2 output, and see how that affects your delay. For more fun see the "DC and switching ..." docs for your target fpga if you haven't already.

 

[FvM]

Outbuf buffer delay should primarly refer to a specification for FPGA family, IO standard, programmed current strength, slew rate settings if applicable, possibly a default capacitive load. None of these are given in your post, so how should we answer about "delay too long"?

We can't say but apparently different from a first guess...

 

[hithesh123]

Outbuf buffer delay should primarly refer to a specification for FPGA family, IO standard, programmed current strength, slew rate settings if applicable, possibly a default capacitive load. None of these are given in your post, so how should we answer about "delay too long"?

We can't say but apparently different from a first guess...

The slew rate, IO standard are same for both input and output signals.
I am trying to find out why OBUF takes nearly 3x the delay compared to IBUF.

After reading your post, I changed the slew from slow to fast only for OBUF and synthesised again. No change.

 

[mrflibble]

The slew rate, IO standard are same for both input and output signals.
I am trying to find out why OBUF takes nearly 3x the delay compared to IBUF.

After reading your post, I changed the slew from slow to fast only for OBUF and synthesised again. No change.

Well that is good to know! What units is "same" in again, I forgot. nanopixies?

Point being, it being the "same" doesn't mean a thing for this set: { World minus hithesh123 }

Other than that. Set SLEW to fast, drive to max whatever it is for your device, and for the fun of it set VCCIO to max, and your signal standard to max wasteful. TTL should do the trick.

And IBUF vs OBUF is vaguely related apples + oranges that happen to be on the same die. Why do you feel that the propagation delay for 2 different physical entities should be the same?

While from the above we can deduce that your "same" == "slow" for slewrate ... what is the "same" for signal standard you are using? Drive strength? Voltage?

Anyways, it probably all boils down to your expectation value of "IBUF delay should be same as OBUF delay". No reason why it should be. You can combine pretty fast inputs with lazy slow outputs if your design happens to call for that.