FPGA internal logic analyzer

[promach]

1. I am using ISE Chipscope ILA as shown in the picture below. May I know how I actually use CONTROL0 and TRIG0 signals to captured the FPGA signal that I want ? Note: I am trying to debug on this DDR memory controller project at https://github.com/promach/DDR

2. I have written my own ILA module at https://github.com/promach/internal_logic_analyzer . However, I am not sure how to code the verilog module that transmits the data to host cpu as well as the cpu software that actually processes the internally captured FPGA signals/data and display them accordingly ?

 

[niciki]

The way I do it in VHDL is as follows:

---

Code VHDL - [expand]
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-- in top
  Chscp_ICON_inst : Chscp_ICON
  port map(
    CONTROL0  => chscp_VIO_top_ctrl,
    CONTROL1  => chscp_ILA_module00_ctrl,
    CONTROL2  => chscp_VIO_module01_ctrl,
    CONTROL3  => chscp_ILA_module01_ctrl
  );
  Chscp_VIO_top_inst : Chscp_VIO_top
  port map(
    CONTROL     => chscp_VIO_top_ctrl,
    ASYNC_IN(31 downto 0)  => BUILD_DATA_G,   --size = 32
    ASYNC_IN(63 downto 32) => VERSION_G,      --size = 32
    ASYNC_IN(95 downto 64) => AUTHOR_G,       --size = 32
    ASYNC_OUT(0) => rst_chscp_vio_top
  );
 
-- in module00
  Chscp_ILA_module00_inst : Chscp_ILA_module00
  port map (
    CONTROL => chscp_ILA_module00_ctrl,
    CLK     => clk100,
    TRIG0(31 downto 0) => some_sig_00,      --size = 32
    TRIG0(32)          => some_sig_01,
    -- ...
    TRIG1(31 downto 0) => some_sig_02,      --size = 32
    TRIG1(32)          => some_sig_03,
    -- ...
    TRIG2(0)  => some_sig_04,
    -- ...
       
    TRIG3(0) => chscp_ILA_module01_trigger_in
  );
 
-- in module01
  Chscp_VIO_module01_inst : Chscp_VIO_module01
  port map(
    CLK         => clk100,
    CONTROL     => chscp_VIO_module01_ctrl,
   
    ASYNC_IN(0)  => some_sig_async_in_00,
    ASYNC_IN(1)  => some_sig_async_in_01,
    ASYNC_IN(2)  => some_sig_async_in_02,
    -- ...
    ASYNC_IN(16)  => some_sig_async_in_16,
    ASYNC_OUT(0) => some_sig_async_out_00,
    SYNC_OUT(0)            => some_sig_sync_out_00,
    SYNC_OUT(1)            => some_sig_sync_out_01,
    SYNC_OUT(2)            => some_sig_sync_out_02,
    SYNC_OUT(12 downto 3)  => some_sig_sync_out_12_03,  --size = 10
    SYNC_OUT(22 downto 13) => some_sig_sync_out_22_13,  --size = 10
   
  );,
  Chscp_ILA_module01_inst : Chscp_ILA_module01
  port map (
    CONTROL => chscp_ILA_module01_ctrl,
    CLK     => clk100,
    TRIG_OUT => Chscp_ILA_module01_trigger_o,
    TRIG0(31 downto 0) => some_sig_00,      --size = 32
    TRIG0(32)          => some_sig_01,
    -- ...
    TRIG1(31 downto 0) => some_sig_02,      --size = 32
    TRIG1(32)          => some_sig_03,
    -- ...
    TRIG2(0)  => some_sig_04,
    -- ...
  );

---

When you now start chipscope and connect to the target, you will see all VIOs and ILAs.
The names of the signals are not preserved as you can see them in VHDL/Verilog. There are three options what you can do:

1. Set names manually in chipscope;
2. Use external script to change .cdc file based of pasted VIO/ILA instantiations in VHDL (this is what I do, but this script is private and not accessible by third-parties);
3. Follow http://www.xilinx.com/support/answers/12281.html for example.

 

[promach]

ALL the ILA modules that I am having now do not work .

I mean they failed to even capture the user-assigned 'clk' and 'resetn' signals. Why ?

Note: the PCB schematics could be found here

 

[niciki]

ila_dq_w - set all X'es in TriggerPort Value and then see what is the nature of this signal. How fast it changes state?

ila_clk won't work, because you used the same signal as sampling clock (CLK) and signal to sample (TRIG0) - think about chipscope as a logic analyser. If the logic analyser is sampling signals at rising edge, then with your configuration it depends on meta-stability and violation of setup/hold times, but I bet you will have always state '1' observed in this case.

ila_reset - from the picture, I can see that the Sample Buffer is full - that means your trigger condition was met (falling edge of resetn) and all 1024 samples was sampled. Please specify what you mean by "not working" in this case. Maybe you can observe all '0' values? If this is the case - change Position to something grater that 0 - let's say 100 (that means from sample 100 you will see that falling edge that caused a trigger).

Show us what waveforms look like.

 

[promach]

> change Position to something grater that 0

@niciki This suggestion solved the issue, it seems. I mean the ILA can capture the signal now.

What I do not understand is how changing the "Position" field actually helps to solve the problem ?
And why the number of samples captured inside the sample buffer == the value of the "Position" field ?

--- Updated May 8, 2021 ---

> ila_dq_w - set all X'es in TriggerPort Value and then see what is the nature of this signal. How fast it changes state?

May I know the purpose of setting all X for trigger value for dq_w ?

 

[promach]

Besides, I am facing sample buffer overfill (at 497241 %) issue which leads to chipscope GUI software non-responding.

How do I CLEAR the sample buffer content ?

 

[niciki]

I mean the ILA can capture the signal now.

What I do not understand is how changing the "Position" field actually helps to solve the problem ?

I wouldn't say that "ILA can capture the signal now" - the truth is that, it sampled the signal also before, but your settings was incorrect to see what you have been expecting on waveform.
What does changing the "Position" in practice? It works as a pre-trigger samples (https://www.tiepie.com/en/fut/pre-trigger). If Position == N, It shows what was happening N samples before the trigger.
Unfortunately datasheet of ILA describes Position IMHO in an unclear way.

And why the number of samples captured inside the sample buffer == the value of the "Position" field ?

It is only true when the trigger is not met. Note that if pre-trigger samples number (i.e. Position) is set at e.g. N samples, all devices like oscilloscopes/logic analysers have to store that N samples before trigger in a circle buffer to show them at the time when the trigger occurs. The device never knows when the trigger will exactly occur, that is why chipscope tells you that the sample buffer == the value of the "Position" field all the time when the trigger is not met.
When the trigger is met, sample buffer will be full (if of course only one window is configured to be captured).

--- Updated May 8, 2021 ---

What changed from last project in ILA0 - now there is 16 bits, the last one there was only one bit?

Note the info about slow or stopped clock.
It is only showed when the chipscope detected too slow clock for the sampling of given signals.
1. Does the CLK connected to valid clock?
2. Does the freq of CLK enough to sample given signals?

Please, to help you more, specify two things:

1. What do you think is not working?
2. What do you expect?

 

[bansalr]

check the clock connection to ILA ..it's not trimmed or stopped...Just open the routed netlist and check.