folded cascode opamp gain

[jimito13]

sutapanaki : Vdsat is defined by the model that "runs" behind a design kit.For example for my process the model is a version of BSIM,so i searched for the Berkeley's manual and i found the definition.It's rather complicated,so i run some parametric simulations with Id vs. Vds (with Vgs parameter) and i saw that the transition from triode to saturation region comes exactly at the point that is defined by the Vdsat parameter of cadence dc operating point results.For long channel devices i have read that Vdsat=Veff=Vod=Vgs-Vth but for short channel devices the definition is different and i suppose is the one defined in each model's manual.In order to be on the safe side i leave a margin of above 50mV (100mV to be absolutely sure as you say!).

steadymind : Many Thanks for the paper.I found it and i am reading it now.

 

[sutapanaki]

You don't mention anything about the type of transition you observed from linear to saturation. Is it a sharp transition or a more gradual one? Did you simulate ro and can you correlate it with the Id vs. Vds curve? I guess these simulations are kind of straying you away from the real design at hand but then on the other hand it is always good to have an idea about the behavior of the transistors you're working with. One more thing, can you compare the values of Vgs-Vth, Vdsat and 2/(gm/Id) ?

 

[jimito13]

I will give you the plot that shows the transition from linear to saturation region.The simulation is for one transistor (with Lmin=100nm) in common source setup and i use Vgs=Vth+200mV (to be in strong inversion).I measure the Id vs. Vds curve for Vds swept from 0 to Vdd (1.2V).The marker on the curve indicates the Vdsat voltage as resulted from Print-->DC Operating Points.

I checked those equations you mentioned and i saw that :

Vdsat≠Vgs-Vth≠(2Id/gm)

I think it was expected for short channel devices...

My second attachment is for the same circuit simulated,that shows the r0 vs. Vds curve.Is this plot expected because i don't know what shape i should see to be sure that everything is ok.

I note that r0=rds=1/gds

Thanks in advance sutapanaki.

 

[diemilio]

I understand that in sub-µm design it's hard to tell when a transistor has transition from Triode to Sat. From your plots I would say that you're in saturation but you can easily tell that your resistance is quite low at the point of operation making me more certain of my first guess, which was that you're just not getting the gain you need cause Ro is not high enough. From your ro vs. Ids (and your Operating point schematic) you can see that none of your transistors has an ro larger than 2 kOhm, which will give you an optimistic output resistance of Ro = 1/2*gmout*ro^2 = 14 kOhm. The total gain of your amp is gmin*Ro = 2.68m*14k = 37.5 which is 31.5 dB. I will even expect your sim results to come out to be much lower cause, as you can see, I neglected a lot of factors (that usually you shouldn't neglect) to calculate the gain.

I will still say that the values you're getting are reasonable... would you agree with me?

 

[jimito13]

How did you calculate this equation : Ro = 1/2*gmout*ro^2 = 14 kOhm ??

My 2 last plots are independent from the design since biasing,L are diffenent from these in the opamp schematic...I just plotted them to see the behavior of the transistors as sutapanaki suggested.

 

[diemilio]

I did a very very coarse approximation...

I just assumed that the ro for the upper and lower branch (lets call it Ro1) of the output node was the same, so Ro = 1/2 of Ro1. Since the output transistors are source-degenerate I approximated their drain resistance to be Ro1=gm*rds*rdsdeg where rds correspond to the output res itself and rdsdeg is the rds of the transistors at the source of the output transistors (I assumed rds=rdsdeg=ro) so that give Ro=1/2*ro^2*gm.

If you wanna use the complete expression then:

Ro = Ro8||Ro6
Ro6 = (rds4||rds2)+rds6*(1+(gm6+gmb6)*(rds4||rds2))
Ro8 = rds10+rds8*(1+(gm8+gmb8)*rds10)

This is gonna give you a much lower value.

Why don't you plot ro vs. Vds for your L and operating point?? That's all you need to get the approx value of your gain! you have gm of the input stage, all you need is Ro!!

May I ask, what is exactly what's bothering you? Is it the fact that your gain is low and you can't explain why, or is it the fact that your gain is low period?

Regards,

diemilio

 

[jimito13]

Ok,it's much more clear now,i just couldn't understand how you came up to this approximation.

The fact that the gain is low bothers me,everyone with this topology reaches above 50dB...for a greater Vdd ofcourse and an older design kit but i don't know where to stop my optimization...i do not want to put more than 2nd stage because i have tried it and it is very difficult to compensate the opamp with nested miller or something like that...

Do you have an approximate value of the input capacitance for a fully diff opamp?
My question is just theoritical so as to have an idea of the order of this capacitance.

Thanks a lot for the answers...

 

[sutapanaki]

This was exactly my point and the reason I asked you to plot those things. As you see the transition is quite gradual and you can't really tell where your triode region ends and your saturation begins. Especially looking at the ro plot. You don't get the max ro until you use unpractical Vds values. This is also the reason why there is a difference between Vgs-Vth, Vdsat and 2/(gm/Id). Usually I go by 2/(gm/Id) as a indicator for saturation although it may come a bit pessimistic.

I will give you the plot that shows the transition from linear to saturation region.The simulation is for one transistor (with Lmin=100nm) in common source setup and i use Vgs=Vth+200mV (to be in strong inversion).I measure the Id vs. Vds curve for Vds swept from 0 to Vdd (1.2V).The marker on the curve indicates the Vdsat voltage as resulted from Print-->DC Operating Points.

I checked those equations you mentioned and i saw that :

Vdsat≠Vgs-Vth≠(2Id/gm)

I think it was expected for short channel devices...

My second attachment is for the same circuit simulated,that shows the r0 vs. Vds curve.Is this plot expected because i don't know what shape i should see to be sure that everything is ok.

I note that r0=rds=1/gds

Thanks in advance sutapanaki.

 

[fishinastorm]

You could make the input PMOS transistors really large, so that they operate in the subthreshold region. Transisotrs in this region have the highest gm for a given bias current. Higher transconductance=higher gain.

 

[jimito13]

yes indeed,i know that...but my application requires high unity gain freq for the opamp,so i cannot operate my transistors in the subthreshold region.

The problem for not taking much more gain for my required UGB is the low Rout of the folded cascode OTA as diemilio noticed above and i confirmed via my simulations.I tried to make Ro larger by making Ids of M5 low (see the first schematic i have posted above to see which transistor is M5) or by increasing L or by tweaking the dc operating point but Phase Margin becomes unacceptable!

I have one final question to close this topic.I follow Allen-Holbers's (and other analog design books) design guide and i make Ids,M5 1.2 to 2 times greater than Ids,M1.All analog design books give a same explanation why we make this assumption for the bias currents.But,does anybody know why this assumption affects Phase Margin??From cadence simulations i notice that when Ids,M5<1.2Ids,M1 Phase Margin becomes unacceptable...

I must say a big thanks to all people that took some time to help me with all my questions. Very Happy

 

[sutapanaki]

I confess, I haven't read the Allen book, but what I can think of is that if you make the current in the cascode branches higher you increase the cascode transistors gm resp. the 1/gm at the cascode source drops and the non-dominant pole moves higher in frequency, so better PM. But then, for modern technologies and small supplies you need to worry about the Vgs of the cascode devices so not to put into triode the transistors below them. So you tend to increase the current but also increase eventually the size and may be you gain nothing or it becomes worse. Allen's book was written years ago when probably 3.3v supply was the mainstream.
Anyway, why don't you try also gain boosted cascodes as someone suggested earlier?

 

[jimito13]

My thoughts were similar with yours about phase margin.But i was wondering if there is another explanation that i miss so that i can reduce power dissipation for my opamp.Definetely i am going to apply the gain boosting technique,it is exactly my next step for this design.Thanks for your help sutapanaki

 

[mengyj0706]

I think allen's book said the current flow in M3 is 1.2 or 2 times the current flow in MB11, but not Im5 = 1.2 or 2 Im1.

 

[jimito13]

Definetely not...check it again and you will see i am right at page 307 of Allen-Holbergs's book and also "Structured Analog CMOS Design" by Kayal,Stefanovic.

 

[mengyj0706]

i dont have kayal book.
I check it again and find that we are the same meaning. p307 said i4(i5)=1.2 or 1.5 times i3, roughly means i5 =1.4 or 2 i1(in your schematic)

 

[jimito13]

exactly! kayal book says the same. you can google it and download it via rapidshare or other uploaders.

 

[upvl]

1. GBW is the critical parameter for Opamp by power constrain. I think increasing L could increase gain to a satisfactory level in your case if you don't care speed so much.
2. You can connect the bulk of PMOS to the source.

 

[Jeekoky]

I must say a big thanks to both of you guys for taking time to deal with my questions

Well,in the picture below i show you my dc operating point as a result of cadence spectre simulator.I hope that the info you asked for are clear from the image...
The circuits in the circles are my biasing networks for the input diff pair.The ideal dc voltage sources are used to provide the proper gate biasing for the transistors since i have not created a biasing network for my opamp yet.In addition,as i mentioned earlier i have not created yet a cmfb network.All transistor work in moderate inversion region (approximately Vgs-Vth≈100mV) and in saturation [from spectre results : Vds>Vdsat (Vds≈Vdsat+100mV or more than 100mV)].The simulations give 30dB of low freq gain and i have no problem with the unity gain freq and phase margin specs.I also do not use any load cap or res.

I would appreciate your opinion for my problem with the dc gain.

From the DC operation points plot, i could say you make a small mistake on the bias current.

You are refered to Allen's book. That's no problem. Yet you need to make the bias current in T1a 1.2~1.5 times the bias current in T1 plus or T1 minus, not the bias current in cascode 1.2~1.5 times. That's to say, the bias current in the cascode should better to be smaller than the bias current in differential pair. It will improve you output impedance and make you DC gain around 40~50dB.

Best regards,

 

[sandeeppemmaraju]

H jimeece13,
I am new to the edaboard. I looked at your circuit posted in your first post.

IMHO ... For folded cascode structure, you cannot bias all the 4 transistor in the cascode structures. You will have to self bias one of the sides. I understand that by doing so, you will only get a single ended output, but you can generate differential output by using buffer stages for Vo+ and Vo-. On top of that, you will have to use CMFB to maintain the differential output nodes at a CM value. Other purpose of using buffers is to get rail to rail output swing.

I am assuming you understand what I meant by self biasing one of the stages, connect the pmos gate of one stage to the drain of the pmos below it, dont source it directly by a bias voltage.

If you use external bias for all transistor in the output stage, you will get low gain due to some transistors entering the triode/linear region.

Also, make sure that your bottom NMOS W/L can sink all of the current from your input PMOS current source. The bottom NMOS W/L are usually sized twice to the other NMOS devices.

Hope this helps.

Thanks.

 

[bilal_e78]

Hi,

I am a very new this analog designing and i am also trying to design the same topology..

I have some problems regarding

1)hOW would i know about , that i have a correct DC operating point. I means what value of the output voltage i should expect if I used Vin+=400mV, Vin=-400mV, what should the Vout+ and Vout- should be
if Dc gain is about 30 dB.

2) I have completly studied your whole post and I m following Structure Analog CMos Design and Razavi's book for sizing of the transistors, but i m getting differnt currents and gm values from calculations.

3) Biasing of the structures, we need some voltages can any one guide what should be the good guessng way,....for starting or should I need a proper biasing circuitry and sam efor the CMFB ciruit.

Vdd = 1.2 V, Vss =0. and my GBW and SR are both very high.

Thanking in advance.
Ans also i am very sorry to start in here,,,,,,,,i thought its very much similar to my problem, hope u dnt mind...


Regards
Bilal


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