FMEDA: MOSFET & BJT floating gate/base

[stenzer]

Hi,

during a FMEDA we came across the failure case "floating gate" and "floating base" for MOSFETs and BJTs, respectively. As this node is considered floating e.g. under the assumption the bonding wire within the package is electrically open (not conductive) there is quite a huge speculation range what can happen e.g. due to the inner structure of the transistor or building-up/down of charge. We already spent several hours discussing this issue.

- So my question is has anybody experience with that, or has any clue how to propperly deal and consider this issue?
- Is there a possebility of simulating this case with a Spice tool to gain somehow "plausible" results (I doubt that)? E.g. LTSpice is considering a gmin value ("Conductance added to every PN junction to aid convergence. "), so already the Spice tool interferes with the transistor model.

I'm thankfull for any advise.
BR

 

[Dominik Przyborowski]

Cadence spectre has dedicated checks for various cases including floating gate detection. For sure hspice and eldo should have the same. No idea whether similar stuff is implemented in free tools.

 

[dick_freebird]

Floating gate MOSFETs are tricky, you can't
control or even know the charge that sits
on the gate electrode. It's basically an EEPROM
cell minus the programming and read
circuitry, open to meddling by every handling
and assembly step, and hot carrier charging
(that is usually an element of the EEPROM
write process, tunneling carriers onto the
gate). So you could expect drain current to
drift, but predicting which way and how much,
forget it.

Open-base BJTs are better behaved, below
BVceo you should see less than the rating's
collector-current test limit (although this is
at room temp, and will surely increase at
high temp). But at voltages less than BVceo
you'd see only low-current-beta times the
C-B junction leakage, which for small signal
transistors in IC technology ought to be a nit.

 

[stenzer]

Hi and thank you for your replies,

Cadence spectre has dedicated checks for various cases including floating gate detection. For sure hspice and eldo should have the same. No idea whether similar stuff is implemented in free tools.

what is meant by floating gate detection? For me it sounds the program checks if there are not connected gates in the schematic, giving no special feedback what migt happen if operated with this condition. According to a quick web search it seems its a ERC result "... provide ERC-like reports for dangling nodes, floating gates, floating bulks, or hot wells. ". I'm more concerned about a rielized PCB including a defect transistor and how it might behave.

Floating gate MOSFETs are tricky, you can't
control or even know the charge that sits
on the gate electrode. It's basically an EEPROM
cell minus the programming and read
circuitry, open to meddling by every handling
and assembly step, and hot carrier charging
(that is usually an element of the EEPROM
write process, tunneling carriers onto the
gate). So you could expect drain current to
drift, but predicting which way and how much,
forget it.

They are really tricky, and the behavior is not predictable and hard to argue during a FMEDA.

Open-base BJTs are better behaved, below
BVceo you should see less than the rating's
collector-current test limit (although this is
at room temp, and will surely increase at
high temp). But at voltages less than BVceo
you'd see only low-current-beta times the
C-B junction leakage, which for small signal
transistors in IC technology ought to be a nit.

My first intention is also a more "predictable" behaviour as a cartain BE voltage difference is required to turn-on the BJT AND there is also a certain amount of base current required to cause a significant collector current. E.g. for a NPN BJT in a low side switch application, i would assume it is turned off. Is this assumption feasable?

BR

 

[Dominik Przyborowski]

what is meant by floating gate detection? For me it sounds the program checks if there are not connected gates in the schematic, giving no special feedback what migt happen if operated with this condition.

Program check whether there is any gate connected to high impedance, so is floating. The case is, that for example in power down mode some transistors might has gate connected to high impedance net (ex. Tri-state buffer or not clamped analog output stage) which forces then exceeding current flow in the circuit. This is one of the possible scenario.

 

[stenzer]

which forces then exceeding current flow in the circuit.

sorry, I do not get this point. Do you mean across the transistor e.g. collector/drain to emitter/source?

 

[Dominik Przyborowski]

Here is a screenshot from spectre manual. Hope it make it clear:

 

[stenzer]

Hi @dick_freebird,

my first intention is also a more "predictable" behaviour for a floating BJT gate as a cartain BE voltage difference is required to turn-on the BJT AND there is also a certain amount of base current required to cause a significant collector current. E.g. for a NPN BJT in a low side switch application, i would assume it is turned off.

Is this assumption feasable?

BR

 

[dick_freebird]

To a point, but you'd need to put a box around
the open-base collector leakage and the load
impedance to say how close you are to "uh, oh".
And realize that activity on that collector node
might provide the energy to turn on the base
(Cjc and node dV/dt).

A deeper question might be, why is there a
device present which can never have a useful
function? Either you're looking too close-in,
and ignoring the larger circuit which might
provide the missing connection, or that BJT
has no good reason for being. In the former
case you'd disposition the "flag" as simple
"looking at the wrong picture". The latter, you'd
ask somebody to provide the reason for that
element being present (maybe leading to
a conclusion that the design again is being
mis-reviewed, or that the design really does
have dumb stuff embedded).

 

[stenzer]

Hi,

A deeper question might be, why is there a
device present which can never have a useful
function?

that's caused by the analyzed FMEDA failure cases, and might be a latent failure if not detected by the diagnostic circuitry.

... or that BJT has no good reason for being.

there might be a good reason for the BJT e.g. if it is part of the diagnostics, but to cover also possible failures within the diagnostics might incrase cost, PCB space and even the FIT rate due to additional components.

Here I'm more concerend abaut how to deal and interprete open gate and base issues, as they are not really predictive in my opinion.

BR