BJT problem circuits

[cupoftea]

Hi,
Do you agree that only circuit A attached is OK? Circuits B and C are at fault?

LTspice and jpeg schem attached

(BTW , unfortunately i cannot post the actual full circuit in each case)

 

[D.A.(Tony)Stewart]

No I do not agree. They are all Ok, but have some redundant parts.

 

[FvM]

The yet given information doesn't substantiate why we need more than one transistor.

 

[danadakk]

B does seem OK as Stewart states.

Circuit C does achieve very high duty cycle, based on delays between the coupled
NPN and PNP pair, but thats a very poor design due to device to device variation
and other T and V effects.

Regards, Dana.

 

[tepalia02]

B does seem OK as Stewart states.

View attachment 185640

Circuit C does achieve very high duty cycle, based on delays between the coupled
NPN and PNP pair, but thats a very poor design due to device to device variation
and other T and V effects.

View attachment 185641


Regards, Dana.

Dear sir/madam, which simulation software did you use here? I guess the name is 'Simplis simulator'. I never heard of it before. Is it something equivalent to the P-spice? Thanks in advance.

 

[danadakk]

Its Simetrix, a PSPICE simulator, with excellent probing capabilities.

It used to be Analog Devices preferred simulator until they bought Linear Technology
who used LTC Spice. In my opinion a bit inferior to Simetrix.

SIMetrix Circuit Design and Simulation

SIMetrix and SIMetrix/SIMPLIS analog and switching-power circuit design and simulation software homepage.

www.simetrix.co.uk

Note in order to show the very fast - going switching in last sim I showed one
has to decrease time increment to 1 or 10 nS. Simple to do.


Regards, Dana.

 

[FvM]

Circuit B is driving Q15 in BE breakdown, in so far Z-diode variant A might be preferred. We don't know if different behaviour of circuit C is intentional or not. As said, we don't have any specification.

Single transistor driver has similar behavior

 

[D.A.(Tony)Stewart]

All ABC are more suited to a weak sinusoidal signal such as 50 to 500 mVp rather than +/-10V which stresses Vebo = 5Vmax (reverse bias)

 

[danadakk]

Circuit C & B do not seem to exhibit and Vebo issues.

Regards, Dana.

 

[cupoftea]

Circuit C does achieve very high duty cycle, based on delays between the coupled
NPN and PNP pair, but thats a very poor design due to device to device variation
and other T and V effects.

Thanks thats exactly what i meant......A npn needs a diode placed with anode to base and cathode to collector....to sweep out charge carriers...in C, this diode is there, but is the wrong way round.....(its the diode in the PNP, ie the base-emitter diode).....so there will be storage time effects which will delay the switching of the BJTs.
As Such, as i think you would agree, C is terrible?

The problem with any spice is that this effect is not modelled.

 

[D.A.(Tony)Stewart]

Given the frequency applied , a clamp diode or base-emitter charge would be equally negligible.
There is no chance of excess reverse voltage with circuit C.

The duty cycle of the narrow negative pulse reduces with increasing input AC signal and hFE. DC offset will make the 1st stage asymmetrical and affect positions of pulse only.

There are no harmful effects of circuit C however like an XOR function will pull up during the dead-band of NPN-PNP pair for Vbe, so also acts as a frequency doubler.

Since Falstad does not analyze storage time effects, I added 22 pF across Vce.