floating well PAD ESD problem?

[gsheng]

when PD/ND mode, there are two paths from pad to Vdd,
(1) PAD->NMOS->VSS->VSS ESD BUS-> Vdd to Vss NMOS(or diode)->Vdd;
(2) PAD->foating well of PMOS ->Vdd;
I don't know which path is the main path. does path 2 exist?

 

[sunking]

why not add a pmos for the charge from PAD to Vdd?

 

[gsheng]

Because the pad is like 3.3V torlance 5V PAD.

Added after 2 hours 5 minutes:

We can not only connect PMOS's bulk to core vdd. Otherwise it will leackage through juntcion diode.

 

[Baiyawfan]

I think if PAD has a negtive ESD voltage,then path (1) is active,else if postive voltage,path (2) is active,right?

 

[ranier]

In case of tolerant I/O ( floating nWell structure), there is no path of pad to vdd .

so path (1) is just available.

 

[gsheng]

In case of tolerant I/O ( floating nWell structure), there is no path of pad to vdd .

so path (1) is just available.

Do you mean path(2) is available? I do want to know why?