Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Finding critical paths in a flip-flop

Status
Not open for further replies.

electronics20

Full Member level 1
Joined
Apr 27, 2011
Messages
99
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,288
Activity points
1,888
Dear scholars and researchers
I dealt with an issue in optimizing a logical gate through finding optimal aspect ratio (for example Flip-Flop) in sub-threshold region. How do I find critical paths in a flip-flop?
Best regards,
 

Hi,
Critical path is the path that has most delay in it in other words if you want create clock signal for your circuit you should wait equal to delay of critical path.for finding that you can find a way with most gates and FF.
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top