Oct 24, 2017 #1 M mahbod72 Newbie level 1 Joined Aug 26, 2017 Messages 0 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 0 Hi friends, I want to know how can I find out the area of sub-modules of a Verilog design using Synopsys design compiler. Please let me know if you have any questions.
Hi friends, I want to know how can I find out the area of sub-modules of a Verilog design using Synopsys design compiler. Please let me know if you have any questions.
Oct 30, 2017 #2 R rca Advanced Member level 5 Joined May 20, 2010 Messages 1,527 Helped 355 Reputation 710 Reaction score 336 Trophy points 1,363 Location Marin Activity points 8,773 report_read -hierarchy With the depth you could have your sub-modules