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Find maximum frequency at quartus

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abd_elhamid_

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I want to know the different (meaning) between the following two parts and how can I find them in quartus through timing analysis
i. The maximum internal clock frequency (clock for registered operation).
ii. The maximum frequency of variation of the input data.


Thanks
 

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I believe under some clock tab in the STA tool it has a rundown on the maximum frequencies of all clocks, i.e. the clock frequency that results in 0 slack for the existing timing constraints. If you don't have timing constraints I thought the tool gave the maximum attainable frequency for the design.

Not sure about the input data one. If it's anything like Xilinx tools you can force the tools to report a datasheet report i.e. an I/O timing report and figure it out from there. If you want a specific I/O timing relationship then you should use constraints.
 

TrickyDicky

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The easiest way to get the Fmax for your clock, just remove your timing contraints, or overconstrain your clock, and check the timequest report. With no timing constraints, it will auto-constrain any signal it thinks is a clock to 1000Mhz, and give you the fmax based on the slow (high temp) and fast (low temp) models - you want the high temp number.

The max frequency of variation of the input data will be the same as your clock?

This all assumes your design is completly synchronous. Timequest cannot work on asynchronous data paths without a lot of timing constraints.

- - - Updated - - -

The easiest way to get the Fmax for your clock, just remove your timing contraints, or overconstrain your clock, and check the timequest report. With no timing constraints, it will auto-constrain any signal it thinks is a clock to 1000Mhz, and give you the fmax based on the slow (high temp) and fast (low temp) models - you want the high temp number.

The max frequency of variation of the input data will be the same as your clock?

This all assumes your design is completly synchronous. Timequest cannot work on asynchronous data paths without a lot of timing constraints.
 

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